/*****************************************************************************
 * File : processing_system7_vip_v1_0_7_reg_init.v
 *
 * Date : 2012-11
 *
 * Description : Initialize register default values.
 *
 *****************************************************************************/

// Register default value info for chip pele_ps
// This code was auto-generated by xregdb.py ver. 0.68, Thu Jul 12 10:32:25 2012
// 54 modules, 2532 registers.


// ************************************************************
//   Module afi0 AFI
//   doc version: 1.1
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( afi0__AFI_RDCHAN_CTRL, val_afi0__AFI_RDCHAN_CTRL);
set_reset_data( afi0__AFI_RDCHAN_ISSUINGCAP, val_afi0__AFI_RDCHAN_ISSUINGCAP);
set_reset_data( afi0__AFI_RDQOS, val_afi0__AFI_RDQOS);
set_reset_data( afi0__AFI_RDDATAFIFO_LEVEL, val_afi0__AFI_RDDATAFIFO_LEVEL);
set_reset_data( afi0__AFI_RDDEBUG, val_afi0__AFI_RDDEBUG);
set_reset_data( afi0__AFI_WRCHAN_CTRL, val_afi0__AFI_WRCHAN_CTRL);
set_reset_data( afi0__AFI_WRCHAN_ISSUINGCAP, val_afi0__AFI_WRCHAN_ISSUINGCAP);
set_reset_data( afi0__AFI_WRQOS, val_afi0__AFI_WRQOS);
set_reset_data( afi0__AFI_WRDATAFIFO_LEVEL, val_afi0__AFI_WRDATAFIFO_LEVEL);
set_reset_data( afi0__AFI_WRDEBUG, val_afi0__AFI_WRDEBUG);

// ************************************************************
//   Module afi1 AFI
//   doc version: 1.1
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( afi1__AFI_RDCHAN_CTRL, val_afi1__AFI_RDCHAN_CTRL);
set_reset_data( afi1__AFI_RDCHAN_ISSUINGCAP, val_afi1__AFI_RDCHAN_ISSUINGCAP);
set_reset_data( afi1__AFI_RDQOS, val_afi1__AFI_RDQOS);
set_reset_data( afi1__AFI_RDDATAFIFO_LEVEL, val_afi1__AFI_RDDATAFIFO_LEVEL);
set_reset_data( afi1__AFI_RDDEBUG, val_afi1__AFI_RDDEBUG);
set_reset_data( afi1__AFI_WRCHAN_CTRL, val_afi1__AFI_WRCHAN_CTRL);
set_reset_data( afi1__AFI_WRCHAN_ISSUINGCAP, val_afi1__AFI_WRCHAN_ISSUINGCAP);
set_reset_data( afi1__AFI_WRQOS, val_afi1__AFI_WRQOS);
set_reset_data( afi1__AFI_WRDATAFIFO_LEVEL, val_afi1__AFI_WRDATAFIFO_LEVEL);
set_reset_data( afi1__AFI_WRDEBUG, val_afi1__AFI_WRDEBUG);

// ************************************************************
//   Module afi2 AFI
//   doc version: 1.1
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( afi2__AFI_RDCHAN_CTRL, val_afi2__AFI_RDCHAN_CTRL);
set_reset_data( afi2__AFI_RDCHAN_ISSUINGCAP, val_afi2__AFI_RDCHAN_ISSUINGCAP);
set_reset_data( afi2__AFI_RDQOS, val_afi2__AFI_RDQOS);
set_reset_data( afi2__AFI_RDDATAFIFO_LEVEL, val_afi2__AFI_RDDATAFIFO_LEVEL);
set_reset_data( afi2__AFI_RDDEBUG, val_afi2__AFI_RDDEBUG);
set_reset_data( afi2__AFI_WRCHAN_CTRL, val_afi2__AFI_WRCHAN_CTRL);
set_reset_data( afi2__AFI_WRCHAN_ISSUINGCAP, val_afi2__AFI_WRCHAN_ISSUINGCAP);
set_reset_data( afi2__AFI_WRQOS, val_afi2__AFI_WRQOS);
set_reset_data( afi2__AFI_WRDATAFIFO_LEVEL, val_afi2__AFI_WRDATAFIFO_LEVEL);
set_reset_data( afi2__AFI_WRDEBUG, val_afi2__AFI_WRDEBUG);

// ************************************************************
//   Module afi3 AFI
//   doc version: 1.1
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( afi3__AFI_RDCHAN_CTRL, val_afi3__AFI_RDCHAN_CTRL);
set_reset_data( afi3__AFI_RDCHAN_ISSUINGCAP, val_afi3__AFI_RDCHAN_ISSUINGCAP);
set_reset_data( afi3__AFI_RDQOS, val_afi3__AFI_RDQOS);
set_reset_data( afi3__AFI_RDDATAFIFO_LEVEL, val_afi3__AFI_RDDATAFIFO_LEVEL);
set_reset_data( afi3__AFI_RDDEBUG, val_afi3__AFI_RDDEBUG);
set_reset_data( afi3__AFI_WRCHAN_CTRL, val_afi3__AFI_WRCHAN_CTRL);
set_reset_data( afi3__AFI_WRCHAN_ISSUINGCAP, val_afi3__AFI_WRCHAN_ISSUINGCAP);
set_reset_data( afi3__AFI_WRQOS, val_afi3__AFI_WRQOS);
set_reset_data( afi3__AFI_WRDATAFIFO_LEVEL, val_afi3__AFI_WRDATAFIFO_LEVEL);
set_reset_data( afi3__AFI_WRDEBUG, val_afi3__AFI_WRDEBUG);

// ************************************************************
//   Module can0 can
//   doc version: 1.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( can0__SRR, val_can0__SRR);
set_reset_data( can0__MSR, val_can0__MSR);
set_reset_data( can0__BRPR, val_can0__BRPR);
set_reset_data( can0__BTR, val_can0__BTR);
set_reset_data( can0__ECR, val_can0__ECR);
set_reset_data( can0__ESR, val_can0__ESR);
set_reset_data( can0__SR, val_can0__SR);
set_reset_data( can0__ISR, val_can0__ISR);
set_reset_data( can0__IER, val_can0__IER);
set_reset_data( can0__ICR, val_can0__ICR);
set_reset_data( can0__TCR, val_can0__TCR);
set_reset_data( can0__WIR, val_can0__WIR);
set_reset_data( can0__TXFIFO_ID, val_can0__TXFIFO_ID);
set_reset_data( can0__TXFIFO_DLC, val_can0__TXFIFO_DLC);
set_reset_data( can0__TXFIFO_DATA1, val_can0__TXFIFO_DATA1);
set_reset_data( can0__TXFIFO_DATA2, val_can0__TXFIFO_DATA2);
set_reset_data( can0__TXHPB_ID, val_can0__TXHPB_ID);
set_reset_data( can0__TXHPB_DLC, val_can0__TXHPB_DLC);
set_reset_data( can0__TXHPB_DATA1, val_can0__TXHPB_DATA1);
set_reset_data( can0__TXHPB_DATA2, val_can0__TXHPB_DATA2);
set_reset_data( can0__RXFIFO_ID, val_can0__RXFIFO_ID);
set_reset_data( can0__RXFIFO_DLC, val_can0__RXFIFO_DLC);
set_reset_data( can0__RXFIFO_DATA1, val_can0__RXFIFO_DATA1);
set_reset_data( can0__RXFIFO_DATA2, val_can0__RXFIFO_DATA2);
set_reset_data( can0__AFR, val_can0__AFR);
set_reset_data( can0__AFMR1, val_can0__AFMR1);
set_reset_data( can0__AFIR1, val_can0__AFIR1);
set_reset_data( can0__AFMR2, val_can0__AFMR2);
set_reset_data( can0__AFIR2, val_can0__AFIR2);
set_reset_data( can0__AFMR3, val_can0__AFMR3);
set_reset_data( can0__AFIR3, val_can0__AFIR3);
set_reset_data( can0__AFMR4, val_can0__AFMR4);
set_reset_data( can0__AFIR4, val_can0__AFIR4);

// ************************************************************
//   Module can1 can
//   doc version: 1.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( can1__SRR, val_can1__SRR);
set_reset_data( can1__MSR, val_can1__MSR);
set_reset_data( can1__BRPR, val_can1__BRPR);
set_reset_data( can1__BTR, val_can1__BTR);
set_reset_data( can1__ECR, val_can1__ECR);
set_reset_data( can1__ESR, val_can1__ESR);
set_reset_data( can1__SR, val_can1__SR);
set_reset_data( can1__ISR, val_can1__ISR);
set_reset_data( can1__IER, val_can1__IER);
set_reset_data( can1__ICR, val_can1__ICR);
set_reset_data( can1__TCR, val_can1__TCR);
set_reset_data( can1__WIR, val_can1__WIR);
set_reset_data( can1__TXFIFO_ID, val_can1__TXFIFO_ID);
set_reset_data( can1__TXFIFO_DLC, val_can1__TXFIFO_DLC);
set_reset_data( can1__TXFIFO_DATA1, val_can1__TXFIFO_DATA1);
set_reset_data( can1__TXFIFO_DATA2, val_can1__TXFIFO_DATA2);
set_reset_data( can1__TXHPB_ID, val_can1__TXHPB_ID);
set_reset_data( can1__TXHPB_DLC, val_can1__TXHPB_DLC);
set_reset_data( can1__TXHPB_DATA1, val_can1__TXHPB_DATA1);
set_reset_data( can1__TXHPB_DATA2, val_can1__TXHPB_DATA2);
set_reset_data( can1__RXFIFO_ID, val_can1__RXFIFO_ID);
set_reset_data( can1__RXFIFO_DLC, val_can1__RXFIFO_DLC);
set_reset_data( can1__RXFIFO_DATA1, val_can1__RXFIFO_DATA1);
set_reset_data( can1__RXFIFO_DATA2, val_can1__RXFIFO_DATA2);
set_reset_data( can1__AFR, val_can1__AFR);
set_reset_data( can1__AFMR1, val_can1__AFMR1);
set_reset_data( can1__AFIR1, val_can1__AFIR1);
set_reset_data( can1__AFMR2, val_can1__AFMR2);
set_reset_data( can1__AFIR2, val_can1__AFIR2);
set_reset_data( can1__AFMR3, val_can1__AFMR3);
set_reset_data( can1__AFIR3, val_can1__AFIR3);
set_reset_data( can1__AFMR4, val_can1__AFMR4);
set_reset_data( can1__AFIR4, val_can1__AFIR4);

// ************************************************************
//   Module ddrc ddrc
//   doc version: 1.25
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( ddrc__ddrc_ctrl, val_ddrc__ddrc_ctrl);
set_reset_data( ddrc__Two_rank_cfg, val_ddrc__Two_rank_cfg);
set_reset_data( ddrc__HPR_reg, val_ddrc__HPR_reg);
set_reset_data( ddrc__LPR_reg, val_ddrc__LPR_reg);
set_reset_data( ddrc__WR_reg, val_ddrc__WR_reg);
set_reset_data( ddrc__DRAM_param_reg0, val_ddrc__DRAM_param_reg0);
set_reset_data( ddrc__DRAM_param_reg1, val_ddrc__DRAM_param_reg1);
set_reset_data( ddrc__DRAM_param_reg2, val_ddrc__DRAM_param_reg2);
set_reset_data( ddrc__DRAM_param_reg3, val_ddrc__DRAM_param_reg3);
set_reset_data( ddrc__DRAM_param_reg4, val_ddrc__DRAM_param_reg4);
set_reset_data( ddrc__DRAM_init_param, val_ddrc__DRAM_init_param);
set_reset_data( ddrc__DRAM_EMR_reg, val_ddrc__DRAM_EMR_reg);
set_reset_data( ddrc__DRAM_EMR_MR_reg, val_ddrc__DRAM_EMR_MR_reg);
set_reset_data( ddrc__DRAM_burst8_rdwr, val_ddrc__DRAM_burst8_rdwr);
set_reset_data( ddrc__DRAM_disable_DQ, val_ddrc__DRAM_disable_DQ);
set_reset_data( ddrc__DRAM_addr_map_bank, val_ddrc__DRAM_addr_map_bank);
set_reset_data( ddrc__DRAM_addr_map_col, val_ddrc__DRAM_addr_map_col);
set_reset_data( ddrc__DRAM_addr_map_row, val_ddrc__DRAM_addr_map_row);
set_reset_data( ddrc__DRAM_ODT_reg, val_ddrc__DRAM_ODT_reg);
set_reset_data( ddrc__phy_dbg_reg, val_ddrc__phy_dbg_reg);
set_reset_data( ddrc__phy_cmd_timeout_rddata_cpt, val_ddrc__phy_cmd_timeout_rddata_cpt);
set_reset_data( ddrc__mode_sts_reg, val_ddrc__mode_sts_reg);
set_reset_data( ddrc__DLL_calib, val_ddrc__DLL_calib);
set_reset_data( ddrc__ODT_delay_hold, val_ddrc__ODT_delay_hold);
set_reset_data( ddrc__ctrl_reg1, val_ddrc__ctrl_reg1);
set_reset_data( ddrc__ctrl_reg2, val_ddrc__ctrl_reg2);
set_reset_data( ddrc__ctrl_reg3, val_ddrc__ctrl_reg3);
set_reset_data( ddrc__ctrl_reg4, val_ddrc__ctrl_reg4);
set_reset_data( ddrc__ctrl_reg5, val_ddrc__ctrl_reg5);
set_reset_data( ddrc__ctrl_reg6, val_ddrc__ctrl_reg6);
set_reset_data( ddrc__CHE_REFRESH_TIMER01, val_ddrc__CHE_REFRESH_TIMER01);
set_reset_data( ddrc__CHE_T_ZQ, val_ddrc__CHE_T_ZQ);
set_reset_data( ddrc__CHE_T_ZQ_Short_Interval_Reg, val_ddrc__CHE_T_ZQ_Short_Interval_Reg);
set_reset_data( ddrc__deep_pwrdwn_reg, val_ddrc__deep_pwrdwn_reg);
set_reset_data( ddrc__reg_2c, val_ddrc__reg_2c);
set_reset_data( ddrc__reg_2d, val_ddrc__reg_2d);
set_reset_data( ddrc__dfi_timing, val_ddrc__dfi_timing);
set_reset_data( ddrc__refresh_timer_2, val_ddrc__refresh_timer_2);
set_reset_data( ddrc__nc_timing, val_ddrc__nc_timing);
set_reset_data( ddrc__CHE_ECC_CONTROL_REG_OFFSET, val_ddrc__CHE_ECC_CONTROL_REG_OFFSET);
set_reset_data( ddrc__CHE_CORR_ECC_LOG_REG_OFFSET, val_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET);
set_reset_data( ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET, val_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET);
set_reset_data( ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET);
set_reset_data( ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET);
set_reset_data( ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET);
set_reset_data( ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET);
set_reset_data( ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET);
set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET);
set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET);
set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET);
set_reset_data( ddrc__CHE_ECC_STATS_REG_OFFSET, val_ddrc__CHE_ECC_STATS_REG_OFFSET);
set_reset_data( ddrc__ECC_scrub, val_ddrc__ECC_scrub);
set_reset_data( ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET, val_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET);
set_reset_data( ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET, val_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET);
set_reset_data( ddrc__phy_rcvr_enable, val_ddrc__phy_rcvr_enable);
set_reset_data( ddrc__PHY_Config0, val_ddrc__PHY_Config0);
set_reset_data( ddrc__PHY_Config1, val_ddrc__PHY_Config1);
set_reset_data( ddrc__PHY_Config2, val_ddrc__PHY_Config2);
set_reset_data( ddrc__PHY_Config3, val_ddrc__PHY_Config3);
set_reset_data( ddrc__phy_init_ratio0, val_ddrc__phy_init_ratio0);
set_reset_data( ddrc__phy_init_ratio1, val_ddrc__phy_init_ratio1);
set_reset_data( ddrc__phy_init_ratio2, val_ddrc__phy_init_ratio2);
set_reset_data( ddrc__phy_init_ratio3, val_ddrc__phy_init_ratio3);
set_reset_data( ddrc__phy_rd_dqs_cfg0, val_ddrc__phy_rd_dqs_cfg0);
set_reset_data( ddrc__phy_rd_dqs_cfg1, val_ddrc__phy_rd_dqs_cfg1);
set_reset_data( ddrc__phy_rd_dqs_cfg2, val_ddrc__phy_rd_dqs_cfg2);
set_reset_data( ddrc__phy_rd_dqs_cfg3, val_ddrc__phy_rd_dqs_cfg3);
set_reset_data( ddrc__phy_wr_dqs_cfg0, val_ddrc__phy_wr_dqs_cfg0);
set_reset_data( ddrc__phy_wr_dqs_cfg1, val_ddrc__phy_wr_dqs_cfg1);
set_reset_data( ddrc__phy_wr_dqs_cfg2, val_ddrc__phy_wr_dqs_cfg2);
set_reset_data( ddrc__phy_wr_dqs_cfg3, val_ddrc__phy_wr_dqs_cfg3);
set_reset_data( ddrc__phy_we_cfg0, val_ddrc__phy_we_cfg0);
set_reset_data( ddrc__phy_we_cfg1, val_ddrc__phy_we_cfg1);
set_reset_data( ddrc__phy_we_cfg2, val_ddrc__phy_we_cfg2);
set_reset_data( ddrc__phy_we_cfg3, val_ddrc__phy_we_cfg3);
set_reset_data( ddrc__wr_data_slv0, val_ddrc__wr_data_slv0);
set_reset_data( ddrc__wr_data_slv1, val_ddrc__wr_data_slv1);
set_reset_data( ddrc__wr_data_slv2, val_ddrc__wr_data_slv2);
set_reset_data( ddrc__wr_data_slv3, val_ddrc__wr_data_slv3);
set_reset_data( ddrc__reg_64, val_ddrc__reg_64);
set_reset_data( ddrc__reg_65, val_ddrc__reg_65);
set_reset_data( ddrc__reg69_6a0, val_ddrc__reg69_6a0);
set_reset_data( ddrc__reg69_6a1, val_ddrc__reg69_6a1);
set_reset_data( ddrc__reg6c_6d2, val_ddrc__reg6c_6d2);
set_reset_data( ddrc__reg6c_6d3, val_ddrc__reg6c_6d3);
set_reset_data( ddrc__reg6e_710, val_ddrc__reg6e_710);
set_reset_data( ddrc__reg6e_711, val_ddrc__reg6e_711);
set_reset_data( ddrc__reg6e_712, val_ddrc__reg6e_712);
set_reset_data( ddrc__reg6e_713, val_ddrc__reg6e_713);
set_reset_data( ddrc__phy_dll_sts0, val_ddrc__phy_dll_sts0);
set_reset_data( ddrc__phy_dll_sts1, val_ddrc__phy_dll_sts1);
set_reset_data( ddrc__phy_dll_sts2, val_ddrc__phy_dll_sts2);
set_reset_data( ddrc__phy_dll_sts3, val_ddrc__phy_dll_sts3);
set_reset_data( ddrc__dll_lock_sts, val_ddrc__dll_lock_sts);
set_reset_data( ddrc__phy_ctrl_sts, val_ddrc__phy_ctrl_sts);
set_reset_data( ddrc__phy_ctrl_sts_reg2, val_ddrc__phy_ctrl_sts_reg2);
set_reset_data( ddrc__axi_id, val_ddrc__axi_id);
set_reset_data( ddrc__page_mask, val_ddrc__page_mask);
set_reset_data( ddrc__axi_priority_wr_port0, val_ddrc__axi_priority_wr_port0);
set_reset_data( ddrc__axi_priority_wr_port1, val_ddrc__axi_priority_wr_port1);
set_reset_data( ddrc__axi_priority_wr_port2, val_ddrc__axi_priority_wr_port2);
set_reset_data( ddrc__axi_priority_wr_port3, val_ddrc__axi_priority_wr_port3);
set_reset_data( ddrc__axi_priority_rd_port0, val_ddrc__axi_priority_rd_port0);
set_reset_data( ddrc__axi_priority_rd_port1, val_ddrc__axi_priority_rd_port1);
set_reset_data( ddrc__axi_priority_rd_port2, val_ddrc__axi_priority_rd_port2);
set_reset_data( ddrc__axi_priority_rd_port3, val_ddrc__axi_priority_rd_port3);
set_reset_data( ddrc__AHB_priority_cfg0, val_ddrc__AHB_priority_cfg0);
set_reset_data( ddrc__AHB_priority_cfg1, val_ddrc__AHB_priority_cfg1);
set_reset_data( ddrc__AHB_priority_cfg2, val_ddrc__AHB_priority_cfg2);
set_reset_data( ddrc__AHB_priority_cfg3, val_ddrc__AHB_priority_cfg3);
set_reset_data( ddrc__perf_mon0, val_ddrc__perf_mon0);
set_reset_data( ddrc__perf_mon1, val_ddrc__perf_mon1);
set_reset_data( ddrc__perf_mon2, val_ddrc__perf_mon2);
set_reset_data( ddrc__perf_mon3, val_ddrc__perf_mon3);
set_reset_data( ddrc__perf_mon20, val_ddrc__perf_mon20);
set_reset_data( ddrc__perf_mon21, val_ddrc__perf_mon21);
set_reset_data( ddrc__perf_mon22, val_ddrc__perf_mon22);
set_reset_data( ddrc__perf_mon23, val_ddrc__perf_mon23);
set_reset_data( ddrc__perf_mon30, val_ddrc__perf_mon30);
set_reset_data( ddrc__perf_mon31, val_ddrc__perf_mon31);
set_reset_data( ddrc__perf_mon32, val_ddrc__perf_mon32);
set_reset_data( ddrc__perf_mon33, val_ddrc__perf_mon33);
set_reset_data( ddrc__trusted_mem_cfg, val_ddrc__trusted_mem_cfg);
set_reset_data( ddrc__excl_access_cfg0, val_ddrc__excl_access_cfg0);
set_reset_data( ddrc__excl_access_cfg1, val_ddrc__excl_access_cfg1);
set_reset_data( ddrc__excl_access_cfg2, val_ddrc__excl_access_cfg2);
set_reset_data( ddrc__excl_access_cfg3, val_ddrc__excl_access_cfg3);
set_reset_data( ddrc__mode_reg_read, val_ddrc__mode_reg_read);
set_reset_data( ddrc__lpddr_ctrl0, val_ddrc__lpddr_ctrl0);
set_reset_data( ddrc__lpddr_ctrl1, val_ddrc__lpddr_ctrl1);
set_reset_data( ddrc__lpddr_ctrl2, val_ddrc__lpddr_ctrl2);
set_reset_data( ddrc__lpddr_ctrl3, val_ddrc__lpddr_ctrl3);
set_reset_data( ddrc__phy_wr_lvl_fsm, val_ddrc__phy_wr_lvl_fsm);
set_reset_data( ddrc__phy_rd_lvl_fsm, val_ddrc__phy_rd_lvl_fsm);
set_reset_data( ddrc__phy_gate_lvl_fsm, val_ddrc__phy_gate_lvl_fsm);

// ************************************************************
//   Module debug_axim axim
//   doc version: 
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( debug_axim__GLOBAL_CTRL, val_debug_axim__GLOBAL_CTRL);
set_reset_data( debug_axim__GLOBAL_STATUS, val_debug_axim__GLOBAL_STATUS);
set_reset_data( debug_axim__FILTER_CTRL, val_debug_axim__FILTER_CTRL);
set_reset_data( debug_axim__TRIGGER_CTRL, val_debug_axim__TRIGGER_CTRL);
set_reset_data( debug_axim__TRIGGER_STATUS, val_debug_axim__TRIGGER_STATUS);
set_reset_data( debug_axim__PACKET_CTRL, val_debug_axim__PACKET_CTRL);
set_reset_data( debug_axim__TOUT_CTRL, val_debug_axim__TOUT_CTRL);
set_reset_data( debug_axim__TOUT_THRESH, val_debug_axim__TOUT_THRESH);
set_reset_data( debug_axim__FIFO_CURRENT, val_debug_axim__FIFO_CURRENT);
set_reset_data( debug_axim__FIFO_HYSTER, val_debug_axim__FIFO_HYSTER);
set_reset_data( debug_axim__SYNC_CURRENT, val_debug_axim__SYNC_CURRENT);
set_reset_data( debug_axim__SYNC_RELOAD, val_debug_axim__SYNC_RELOAD);
set_reset_data( debug_axim__TSTMP_CURRENT, val_debug_axim__TSTMP_CURRENT);
set_reset_data( debug_axim__ADDR0_MASK, val_debug_axim__ADDR0_MASK);
set_reset_data( debug_axim__ADDR0_LOWER, val_debug_axim__ADDR0_LOWER);
set_reset_data( debug_axim__ADDR0_UPPER, val_debug_axim__ADDR0_UPPER);
set_reset_data( debug_axim__ADDR0_MISC, val_debug_axim__ADDR0_MISC);
set_reset_data( debug_axim__ADDR1_MASK, val_debug_axim__ADDR1_MASK);
set_reset_data( debug_axim__ADDR1_LOWER, val_debug_axim__ADDR1_LOWER);
set_reset_data( debug_axim__ADDR1_UPPER, val_debug_axim__ADDR1_UPPER);
set_reset_data( debug_axim__ADDR1_MISC, val_debug_axim__ADDR1_MISC);
set_reset_data( debug_axim__ADDR2_MASK, val_debug_axim__ADDR2_MASK);
set_reset_data( debug_axim__ADDR2_LOWER, val_debug_axim__ADDR2_LOWER);
set_reset_data( debug_axim__ADDR2_UPPER, val_debug_axim__ADDR2_UPPER);
set_reset_data( debug_axim__ADDR2_MISC, val_debug_axim__ADDR2_MISC);
set_reset_data( debug_axim__ADDR3_MASK, val_debug_axim__ADDR3_MASK);
set_reset_data( debug_axim__ADDR3_LOWER, val_debug_axim__ADDR3_LOWER);
set_reset_data( debug_axim__ADDR3_UPPER, val_debug_axim__ADDR3_UPPER);
set_reset_data( debug_axim__ADDR3_MISC, val_debug_axim__ADDR3_MISC);
set_reset_data( debug_axim__ID0_MASK, val_debug_axim__ID0_MASK);
set_reset_data( debug_axim__ID0_LOWER, val_debug_axim__ID0_LOWER);
set_reset_data( debug_axim__ID0_UPPER, val_debug_axim__ID0_UPPER);
set_reset_data( debug_axim__ID0_MISC, val_debug_axim__ID0_MISC);
set_reset_data( debug_axim__ID1_MASK, val_debug_axim__ID1_MASK);
set_reset_data( debug_axim__ID1_LOWER, val_debug_axim__ID1_LOWER);
set_reset_data( debug_axim__ID1_UPPER, val_debug_axim__ID1_UPPER);
set_reset_data( debug_axim__ID1_MISC, val_debug_axim__ID1_MISC);
set_reset_data( debug_axim__ID2_MASK, val_debug_axim__ID2_MASK);
set_reset_data( debug_axim__ID2_LOWER, val_debug_axim__ID2_LOWER);
set_reset_data( debug_axim__ID2_UPPER, val_debug_axim__ID2_UPPER);
set_reset_data( debug_axim__ID2_MISC, val_debug_axim__ID2_MISC);
set_reset_data( debug_axim__ID3_MASK, val_debug_axim__ID3_MASK);
set_reset_data( debug_axim__ID3_LOWER, val_debug_axim__ID3_LOWER);
set_reset_data( debug_axim__ID3_UPPER, val_debug_axim__ID3_UPPER);
set_reset_data( debug_axim__ID3_MISC, val_debug_axim__ID3_MISC);
set_reset_data( debug_axim__AXI_SEL, val_debug_axim__AXI_SEL);
set_reset_data( debug_axim__IT_TRIGOUT, val_debug_axim__IT_TRIGOUT);
set_reset_data( debug_axim__IT_TRIGOUTACK, val_debug_axim__IT_TRIGOUTACK);
set_reset_data( debug_axim__IT_TRIGIN, val_debug_axim__IT_TRIGIN);
set_reset_data( debug_axim__IT_TRIGINACK, val_debug_axim__IT_TRIGINACK);
set_reset_data( debug_axim__IT_ATBDATA, val_debug_axim__IT_ATBDATA);
set_reset_data( debug_axim__IT_ATBSTATUS, val_debug_axim__IT_ATBSTATUS);
set_reset_data( debug_axim__IT_ATBCTRL1, val_debug_axim__IT_ATBCTRL1);
set_reset_data( debug_axim__IT_ATBCTRL0, val_debug_axim__IT_ATBCTRL0);
set_reset_data( debug_axim__IT_CTRL, val_debug_axim__IT_CTRL);
set_reset_data( debug_axim__CLAIM_SET, val_debug_axim__CLAIM_SET);
set_reset_data( debug_axim__CLAIM_CLEAR, val_debug_axim__CLAIM_CLEAR);
set_reset_data( debug_axim__LOCK_ACCESS, val_debug_axim__LOCK_ACCESS);
set_reset_data( debug_axim__LOCK_STATUS, val_debug_axim__LOCK_STATUS);
set_reset_data( debug_axim__AUTH_STATUS, val_debug_axim__AUTH_STATUS);
set_reset_data( debug_axim__DEV_ID, val_debug_axim__DEV_ID);
set_reset_data( debug_axim__DEV_TYPE, val_debug_axim__DEV_TYPE);
set_reset_data( debug_axim__PERIPHID4, val_debug_axim__PERIPHID4);
set_reset_data( debug_axim__PERIPHID5, val_debug_axim__PERIPHID5);
set_reset_data( debug_axim__PERIPHID6, val_debug_axim__PERIPHID6);
set_reset_data( debug_axim__PERIPHID7, val_debug_axim__PERIPHID7);
set_reset_data( debug_axim__PERIPHID0, val_debug_axim__PERIPHID0);
set_reset_data( debug_axim__PERIPHID1, val_debug_axim__PERIPHID1);
set_reset_data( debug_axim__PERIPHID2, val_debug_axim__PERIPHID2);
set_reset_data( debug_axim__PERIPHID3, val_debug_axim__PERIPHID3);
set_reset_data( debug_axim__COMPID0, val_debug_axim__COMPID0);
set_reset_data( debug_axim__COMPID1, val_debug_axim__COMPID1);
set_reset_data( debug_axim__COMPID2, val_debug_axim__COMPID2);
set_reset_data( debug_axim__COMPID3, val_debug_axim__COMPID3);

// ************************************************************
//   Module debug_cpu_cti0 cti
//   doc version: 
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( debug_cpu_cti0__CTICONTROL, val_debug_cpu_cti0__CTICONTROL);
set_reset_data( debug_cpu_cti0__CTIINTACK, val_debug_cpu_cti0__CTIINTACK);
set_reset_data( debug_cpu_cti0__CTIAPPSET, val_debug_cpu_cti0__CTIAPPSET);
set_reset_data( debug_cpu_cti0__CTIAPPCLEAR, val_debug_cpu_cti0__CTIAPPCLEAR);
set_reset_data( debug_cpu_cti0__CTIAPPPULSE, val_debug_cpu_cti0__CTIAPPPULSE);
set_reset_data( debug_cpu_cti0__CTIINEN0, val_debug_cpu_cti0__CTIINEN0);
set_reset_data( debug_cpu_cti0__CTIINEN1, val_debug_cpu_cti0__CTIINEN1);
set_reset_data( debug_cpu_cti0__CTIINEN2, val_debug_cpu_cti0__CTIINEN2);
set_reset_data( debug_cpu_cti0__CTIINEN3, val_debug_cpu_cti0__CTIINEN3);
set_reset_data( debug_cpu_cti0__CTIINEN4, val_debug_cpu_cti0__CTIINEN4);
set_reset_data( debug_cpu_cti0__CTIINEN5, val_debug_cpu_cti0__CTIINEN5);
set_reset_data( debug_cpu_cti0__CTIINEN6, val_debug_cpu_cti0__CTIINEN6);
set_reset_data( debug_cpu_cti0__CTIINEN7, val_debug_cpu_cti0__CTIINEN7);
set_reset_data( debug_cpu_cti0__CTIOUTEN0, val_debug_cpu_cti0__CTIOUTEN0);
set_reset_data( debug_cpu_cti0__CTIOUTEN1, val_debug_cpu_cti0__CTIOUTEN1);
set_reset_data( debug_cpu_cti0__CTIOUTEN2, val_debug_cpu_cti0__CTIOUTEN2);
set_reset_data( debug_cpu_cti0__CTIOUTEN3, val_debug_cpu_cti0__CTIOUTEN3);
set_reset_data( debug_cpu_cti0__CTIOUTEN4, val_debug_cpu_cti0__CTIOUTEN4);
set_reset_data( debug_cpu_cti0__CTIOUTEN5, val_debug_cpu_cti0__CTIOUTEN5);
set_reset_data( debug_cpu_cti0__CTIOUTEN6, val_debug_cpu_cti0__CTIOUTEN6);
set_reset_data( debug_cpu_cti0__CTIOUTEN7, val_debug_cpu_cti0__CTIOUTEN7);
set_reset_data( debug_cpu_cti0__CTITRIGINSTATUS, val_debug_cpu_cti0__CTITRIGINSTATUS);
set_reset_data( debug_cpu_cti0__CTITRIGOUTSTATUS, val_debug_cpu_cti0__CTITRIGOUTSTATUS);
set_reset_data( debug_cpu_cti0__CTICHINSTATUS, val_debug_cpu_cti0__CTICHINSTATUS);
set_reset_data( debug_cpu_cti0__CTICHOUTSTATUS, val_debug_cpu_cti0__CTICHOUTSTATUS);
set_reset_data( debug_cpu_cti0__CTIGATE, val_debug_cpu_cti0__CTIGATE);
set_reset_data( debug_cpu_cti0__ASICCTL, val_debug_cpu_cti0__ASICCTL);
set_reset_data( debug_cpu_cti0__ITCHINACK, val_debug_cpu_cti0__ITCHINACK);
set_reset_data( debug_cpu_cti0__ITTRIGINACK, val_debug_cpu_cti0__ITTRIGINACK);
set_reset_data( debug_cpu_cti0__ITCHOUT, val_debug_cpu_cti0__ITCHOUT);
set_reset_data( debug_cpu_cti0__ITTRIGOUT, val_debug_cpu_cti0__ITTRIGOUT);
set_reset_data( debug_cpu_cti0__ITCHOUTACK, val_debug_cpu_cti0__ITCHOUTACK);
set_reset_data( debug_cpu_cti0__ITTRIGOUTACK, val_debug_cpu_cti0__ITTRIGOUTACK);
set_reset_data( debug_cpu_cti0__ITCHIN, val_debug_cpu_cti0__ITCHIN);
set_reset_data( debug_cpu_cti0__ITTRIGIN, val_debug_cpu_cti0__ITTRIGIN);
set_reset_data( debug_cpu_cti0__ITCTRL, val_debug_cpu_cti0__ITCTRL);
set_reset_data( debug_cpu_cti0__CTSR, val_debug_cpu_cti0__CTSR);
set_reset_data( debug_cpu_cti0__CTCR, val_debug_cpu_cti0__CTCR);
set_reset_data( debug_cpu_cti0__LAR, val_debug_cpu_cti0__LAR);
set_reset_data( debug_cpu_cti0__LSR, val_debug_cpu_cti0__LSR);
set_reset_data( debug_cpu_cti0__ASR, val_debug_cpu_cti0__ASR);
set_reset_data( debug_cpu_cti0__DEVID, val_debug_cpu_cti0__DEVID);
set_reset_data( debug_cpu_cti0__DTIR, val_debug_cpu_cti0__DTIR);
set_reset_data( debug_cpu_cti0__PERIPHID4, val_debug_cpu_cti0__PERIPHID4);
set_reset_data( debug_cpu_cti0__PERIPHID5, val_debug_cpu_cti0__PERIPHID5);
set_reset_data( debug_cpu_cti0__PERIPHID6, val_debug_cpu_cti0__PERIPHID6);
set_reset_data( debug_cpu_cti0__PERIPHID7, val_debug_cpu_cti0__PERIPHID7);
set_reset_data( debug_cpu_cti0__PERIPHID0, val_debug_cpu_cti0__PERIPHID0);
set_reset_data( debug_cpu_cti0__PERIPHID1, val_debug_cpu_cti0__PERIPHID1);
set_reset_data( debug_cpu_cti0__PERIPHID2, val_debug_cpu_cti0__PERIPHID2);
set_reset_data( debug_cpu_cti0__PERIPHID3, val_debug_cpu_cti0__PERIPHID3);
set_reset_data( debug_cpu_cti0__COMPID0, val_debug_cpu_cti0__COMPID0);
set_reset_data( debug_cpu_cti0__COMPID1, val_debug_cpu_cti0__COMPID1);
set_reset_data( debug_cpu_cti0__COMPID2, val_debug_cpu_cti0__COMPID2);
set_reset_data( debug_cpu_cti0__COMPID3, val_debug_cpu_cti0__COMPID3);

// ************************************************************
//   Module debug_cpu_cti1 cti
//   doc version: 
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( debug_cpu_cti1__CTICONTROL, val_debug_cpu_cti1__CTICONTROL);
set_reset_data( debug_cpu_cti1__CTIINTACK, val_debug_cpu_cti1__CTIINTACK);
set_reset_data( debug_cpu_cti1__CTIAPPSET, val_debug_cpu_cti1__CTIAPPSET);
set_reset_data( debug_cpu_cti1__CTIAPPCLEAR, val_debug_cpu_cti1__CTIAPPCLEAR);
set_reset_data( debug_cpu_cti1__CTIAPPPULSE, val_debug_cpu_cti1__CTIAPPPULSE);
set_reset_data( debug_cpu_cti1__CTIINEN0, val_debug_cpu_cti1__CTIINEN0);
set_reset_data( debug_cpu_cti1__CTIINEN1, val_debug_cpu_cti1__CTIINEN1);
set_reset_data( debug_cpu_cti1__CTIINEN2, val_debug_cpu_cti1__CTIINEN2);
set_reset_data( debug_cpu_cti1__CTIINEN3, val_debug_cpu_cti1__CTIINEN3);
set_reset_data( debug_cpu_cti1__CTIINEN4, val_debug_cpu_cti1__CTIINEN4);
set_reset_data( debug_cpu_cti1__CTIINEN5, val_debug_cpu_cti1__CTIINEN5);
set_reset_data( debug_cpu_cti1__CTIINEN6, val_debug_cpu_cti1__CTIINEN6);
set_reset_data( debug_cpu_cti1__CTIINEN7, val_debug_cpu_cti1__CTIINEN7);
set_reset_data( debug_cpu_cti1__CTIOUTEN0, val_debug_cpu_cti1__CTIOUTEN0);
set_reset_data( debug_cpu_cti1__CTIOUTEN1, val_debug_cpu_cti1__CTIOUTEN1);
set_reset_data( debug_cpu_cti1__CTIOUTEN2, val_debug_cpu_cti1__CTIOUTEN2);
set_reset_data( debug_cpu_cti1__CTIOUTEN3, val_debug_cpu_cti1__CTIOUTEN3);
set_reset_data( debug_cpu_cti1__CTIOUTEN4, val_debug_cpu_cti1__CTIOUTEN4);
set_reset_data( debug_cpu_cti1__CTIOUTEN5, val_debug_cpu_cti1__CTIOUTEN5);
set_reset_data( debug_cpu_cti1__CTIOUTEN6, val_debug_cpu_cti1__CTIOUTEN6);
set_reset_data( debug_cpu_cti1__CTIOUTEN7, val_debug_cpu_cti1__CTIOUTEN7);
set_reset_data( debug_cpu_cti1__CTITRIGINSTATUS, val_debug_cpu_cti1__CTITRIGINSTATUS);
set_reset_data( debug_cpu_cti1__CTITRIGOUTSTATUS, val_debug_cpu_cti1__CTITRIGOUTSTATUS);
set_reset_data( debug_cpu_cti1__CTICHINSTATUS, val_debug_cpu_cti1__CTICHINSTATUS);
set_reset_data( debug_cpu_cti1__CTICHOUTSTATUS, val_debug_cpu_cti1__CTICHOUTSTATUS);
set_reset_data( debug_cpu_cti1__CTIGATE, val_debug_cpu_cti1__CTIGATE);
set_reset_data( debug_cpu_cti1__ASICCTL, val_debug_cpu_cti1__ASICCTL);
set_reset_data( debug_cpu_cti1__ITCHINACK, val_debug_cpu_cti1__ITCHINACK);
set_reset_data( debug_cpu_cti1__ITTRIGINACK, val_debug_cpu_cti1__ITTRIGINACK);
set_reset_data( debug_cpu_cti1__ITCHOUT, val_debug_cpu_cti1__ITCHOUT);
set_reset_data( debug_cpu_cti1__ITTRIGOUT, val_debug_cpu_cti1__ITTRIGOUT);
set_reset_data( debug_cpu_cti1__ITCHOUTACK, val_debug_cpu_cti1__ITCHOUTACK);
set_reset_data( debug_cpu_cti1__ITTRIGOUTACK, val_debug_cpu_cti1__ITTRIGOUTACK);
set_reset_data( debug_cpu_cti1__ITCHIN, val_debug_cpu_cti1__ITCHIN);
set_reset_data( debug_cpu_cti1__ITTRIGIN, val_debug_cpu_cti1__ITTRIGIN);
set_reset_data( debug_cpu_cti1__ITCTRL, val_debug_cpu_cti1__ITCTRL);
set_reset_data( debug_cpu_cti1__CTSR, val_debug_cpu_cti1__CTSR);
set_reset_data( debug_cpu_cti1__CTCR, val_debug_cpu_cti1__CTCR);
set_reset_data( debug_cpu_cti1__LAR, val_debug_cpu_cti1__LAR);
set_reset_data( debug_cpu_cti1__LSR, val_debug_cpu_cti1__LSR);
set_reset_data( debug_cpu_cti1__ASR, val_debug_cpu_cti1__ASR);
set_reset_data( debug_cpu_cti1__DEVID, val_debug_cpu_cti1__DEVID);
set_reset_data( debug_cpu_cti1__DTIR, val_debug_cpu_cti1__DTIR);
set_reset_data( debug_cpu_cti1__PERIPHID4, val_debug_cpu_cti1__PERIPHID4);
set_reset_data( debug_cpu_cti1__PERIPHID5, val_debug_cpu_cti1__PERIPHID5);
set_reset_data( debug_cpu_cti1__PERIPHID6, val_debug_cpu_cti1__PERIPHID6);
set_reset_data( debug_cpu_cti1__PERIPHID7, val_debug_cpu_cti1__PERIPHID7);
set_reset_data( debug_cpu_cti1__PERIPHID0, val_debug_cpu_cti1__PERIPHID0);
set_reset_data( debug_cpu_cti1__PERIPHID1, val_debug_cpu_cti1__PERIPHID1);
set_reset_data( debug_cpu_cti1__PERIPHID2, val_debug_cpu_cti1__PERIPHID2);
set_reset_data( debug_cpu_cti1__PERIPHID3, val_debug_cpu_cti1__PERIPHID3);
set_reset_data( debug_cpu_cti1__COMPID0, val_debug_cpu_cti1__COMPID0);
set_reset_data( debug_cpu_cti1__COMPID1, val_debug_cpu_cti1__COMPID1);
set_reset_data( debug_cpu_cti1__COMPID2, val_debug_cpu_cti1__COMPID2);
set_reset_data( debug_cpu_cti1__COMPID3, val_debug_cpu_cti1__COMPID3);

// ************************************************************
//   Module debug_cpu_pmu0 cortexa9_pmu
//   doc version: 1.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( debug_cpu_pmu0__PMXEVCNTR0, val_debug_cpu_pmu0__PMXEVCNTR0);
set_reset_data( debug_cpu_pmu0__PMXEVCNTR1, val_debug_cpu_pmu0__PMXEVCNTR1);
set_reset_data( debug_cpu_pmu0__PMXEVCNTR2, val_debug_cpu_pmu0__PMXEVCNTR2);
set_reset_data( debug_cpu_pmu0__PMXEVCNTR3, val_debug_cpu_pmu0__PMXEVCNTR3);
set_reset_data( debug_cpu_pmu0__PMXEVCNTR4, val_debug_cpu_pmu0__PMXEVCNTR4);
set_reset_data( debug_cpu_pmu0__PMXEVCNTR5, val_debug_cpu_pmu0__PMXEVCNTR5);
set_reset_data( debug_cpu_pmu0__PMCCNTR, val_debug_cpu_pmu0__PMCCNTR);
set_reset_data( debug_cpu_pmu0__PMXEVTYPER0, val_debug_cpu_pmu0__PMXEVTYPER0);
set_reset_data( debug_cpu_pmu0__PMXEVTYPER1, val_debug_cpu_pmu0__PMXEVTYPER1);
set_reset_data( debug_cpu_pmu0__PMXEVTYPER2, val_debug_cpu_pmu0__PMXEVTYPER2);
set_reset_data( debug_cpu_pmu0__PMXEVTYPER3, val_debug_cpu_pmu0__PMXEVTYPER3);
set_reset_data( debug_cpu_pmu0__PMXEVTYPER4, val_debug_cpu_pmu0__PMXEVTYPER4);
set_reset_data( debug_cpu_pmu0__PMXEVTYPER5, val_debug_cpu_pmu0__PMXEVTYPER5);
set_reset_data( debug_cpu_pmu0__PMCNTENSET, val_debug_cpu_pmu0__PMCNTENSET);
set_reset_data( debug_cpu_pmu0__PMCNTENCLR, val_debug_cpu_pmu0__PMCNTENCLR);
set_reset_data( debug_cpu_pmu0__PMINTENSET, val_debug_cpu_pmu0__PMINTENSET);
set_reset_data( debug_cpu_pmu0__PMINTENCLR, val_debug_cpu_pmu0__PMINTENCLR);
set_reset_data( debug_cpu_pmu0__PMOVSR, val_debug_cpu_pmu0__PMOVSR);
set_reset_data( debug_cpu_pmu0__PMSWINC, val_debug_cpu_pmu0__PMSWINC);
set_reset_data( debug_cpu_pmu0__PMCR, val_debug_cpu_pmu0__PMCR);
set_reset_data( debug_cpu_pmu0__PMUSERENR, val_debug_cpu_pmu0__PMUSERENR);

// ************************************************************
//   Module debug_cpu_pmu1 cortexa9_pmu
//   doc version: 1.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( debug_cpu_pmu1__PMXEVCNTR0, val_debug_cpu_pmu1__PMXEVCNTR0);
set_reset_data( debug_cpu_pmu1__PMXEVCNTR1, val_debug_cpu_pmu1__PMXEVCNTR1);
set_reset_data( debug_cpu_pmu1__PMXEVCNTR2, val_debug_cpu_pmu1__PMXEVCNTR2);
set_reset_data( debug_cpu_pmu1__PMXEVCNTR3, val_debug_cpu_pmu1__PMXEVCNTR3);
set_reset_data( debug_cpu_pmu1__PMXEVCNTR4, val_debug_cpu_pmu1__PMXEVCNTR4);
set_reset_data( debug_cpu_pmu1__PMXEVCNTR5, val_debug_cpu_pmu1__PMXEVCNTR5);
set_reset_data( debug_cpu_pmu1__PMCCNTR, val_debug_cpu_pmu1__PMCCNTR);
set_reset_data( debug_cpu_pmu1__PMXEVTYPER0, val_debug_cpu_pmu1__PMXEVTYPER0);
set_reset_data( debug_cpu_pmu1__PMXEVTYPER1, val_debug_cpu_pmu1__PMXEVTYPER1);
set_reset_data( debug_cpu_pmu1__PMXEVTYPER2, val_debug_cpu_pmu1__PMXEVTYPER2);
set_reset_data( debug_cpu_pmu1__PMXEVTYPER3, val_debug_cpu_pmu1__PMXEVTYPER3);
set_reset_data( debug_cpu_pmu1__PMXEVTYPER4, val_debug_cpu_pmu1__PMXEVTYPER4);
set_reset_data( debug_cpu_pmu1__PMXEVTYPER5, val_debug_cpu_pmu1__PMXEVTYPER5);
set_reset_data( debug_cpu_pmu1__PMCNTENSET, val_debug_cpu_pmu1__PMCNTENSET);
set_reset_data( debug_cpu_pmu1__PMCNTENCLR, val_debug_cpu_pmu1__PMCNTENCLR);
set_reset_data( debug_cpu_pmu1__PMINTENSET, val_debug_cpu_pmu1__PMINTENSET);
set_reset_data( debug_cpu_pmu1__PMINTENCLR, val_debug_cpu_pmu1__PMINTENCLR);
set_reset_data( debug_cpu_pmu1__PMOVSR, val_debug_cpu_pmu1__PMOVSR);
set_reset_data( debug_cpu_pmu1__PMSWINC, val_debug_cpu_pmu1__PMSWINC);
set_reset_data( debug_cpu_pmu1__PMCR, val_debug_cpu_pmu1__PMCR);
set_reset_data( debug_cpu_pmu1__PMUSERENR, val_debug_cpu_pmu1__PMUSERENR);

// ************************************************************
//   Module debug_cpu_ptm0 ptm
//   doc version: 
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( debug_cpu_ptm0__ETMCR, val_debug_cpu_ptm0__ETMCR);
set_reset_data( debug_cpu_ptm0__ETMCCR, val_debug_cpu_ptm0__ETMCCR);
set_reset_data( debug_cpu_ptm0__ETMTRIGGER, val_debug_cpu_ptm0__ETMTRIGGER);
set_reset_data( debug_cpu_ptm0__ETMSR, val_debug_cpu_ptm0__ETMSR);
set_reset_data( debug_cpu_ptm0__ETMSCR, val_debug_cpu_ptm0__ETMSCR);
set_reset_data( debug_cpu_ptm0__ETMTSSCR, val_debug_cpu_ptm0__ETMTSSCR);
set_reset_data( debug_cpu_ptm0__ETMTECR1, val_debug_cpu_ptm0__ETMTECR1);
set_reset_data( debug_cpu_ptm0__ETMACVR1, val_debug_cpu_ptm0__ETMACVR1);
set_reset_data( debug_cpu_ptm0__ETMACVR2, val_debug_cpu_ptm0__ETMACVR2);
set_reset_data( debug_cpu_ptm0__ETMACVR3, val_debug_cpu_ptm0__ETMACVR3);
set_reset_data( debug_cpu_ptm0__ETMACVR4, val_debug_cpu_ptm0__ETMACVR4);
set_reset_data( debug_cpu_ptm0__ETMACVR5, val_debug_cpu_ptm0__ETMACVR5);
set_reset_data( debug_cpu_ptm0__ETMACVR6, val_debug_cpu_ptm0__ETMACVR6);
set_reset_data( debug_cpu_ptm0__ETMACVR7, val_debug_cpu_ptm0__ETMACVR7);
set_reset_data( debug_cpu_ptm0__ETMACVR8, val_debug_cpu_ptm0__ETMACVR8);
set_reset_data( debug_cpu_ptm0__ETMACTR1, val_debug_cpu_ptm0__ETMACTR1);
set_reset_data( debug_cpu_ptm0__ETMACTR2, val_debug_cpu_ptm0__ETMACTR2);
set_reset_data( debug_cpu_ptm0__ETMACTR3, val_debug_cpu_ptm0__ETMACTR3);
set_reset_data( debug_cpu_ptm0__ETMACTR4, val_debug_cpu_ptm0__ETMACTR4);
set_reset_data( debug_cpu_ptm0__ETMACTR5, val_debug_cpu_ptm0__ETMACTR5);
set_reset_data( debug_cpu_ptm0__ETMACTR6, val_debug_cpu_ptm0__ETMACTR6);
set_reset_data( debug_cpu_ptm0__ETMACTR7, val_debug_cpu_ptm0__ETMACTR7);
set_reset_data( debug_cpu_ptm0__ETMACTR8, val_debug_cpu_ptm0__ETMACTR8);
set_reset_data( debug_cpu_ptm0__ETMCNTRLDVR1, val_debug_cpu_ptm0__ETMCNTRLDVR1);
set_reset_data( debug_cpu_ptm0__ETMCNTRLDVR2, val_debug_cpu_ptm0__ETMCNTRLDVR2);
set_reset_data( debug_cpu_ptm0__ETMCNTENR1, val_debug_cpu_ptm0__ETMCNTENR1);
set_reset_data( debug_cpu_ptm0__ETMCNTENR2, val_debug_cpu_ptm0__ETMCNTENR2);
set_reset_data( debug_cpu_ptm0__ETMCNTRLDEVR1, val_debug_cpu_ptm0__ETMCNTRLDEVR1);
set_reset_data( debug_cpu_ptm0__ETMCNTRLDEVR2, val_debug_cpu_ptm0__ETMCNTRLDEVR2);
set_reset_data( debug_cpu_ptm0__ETMCNTVR1, val_debug_cpu_ptm0__ETMCNTVR1);
set_reset_data( debug_cpu_ptm0__ETMCNTVR2, val_debug_cpu_ptm0__ETMCNTVR2);
set_reset_data( debug_cpu_ptm0__ETMSQ12EVR, val_debug_cpu_ptm0__ETMSQ12EVR);
set_reset_data( debug_cpu_ptm0__ETMSQ21EVR, val_debug_cpu_ptm0__ETMSQ21EVR);
set_reset_data( debug_cpu_ptm0__ETMSQ23EVR, val_debug_cpu_ptm0__ETMSQ23EVR);
set_reset_data( debug_cpu_ptm0__ETMSQ31EVR, val_debug_cpu_ptm0__ETMSQ31EVR);
set_reset_data( debug_cpu_ptm0__ETMSQ32EVR, val_debug_cpu_ptm0__ETMSQ32EVR);
set_reset_data( debug_cpu_ptm0__ETMSQ13EVR, val_debug_cpu_ptm0__ETMSQ13EVR);
set_reset_data( debug_cpu_ptm0__ETMSQR, val_debug_cpu_ptm0__ETMSQR);
set_reset_data( debug_cpu_ptm0__ETMEXTOUTEVR1, val_debug_cpu_ptm0__ETMEXTOUTEVR1);
set_reset_data( debug_cpu_ptm0__ETMEXTOUTEVR2, val_debug_cpu_ptm0__ETMEXTOUTEVR2);
set_reset_data( debug_cpu_ptm0__ETMCIDCVR1, val_debug_cpu_ptm0__ETMCIDCVR1);
set_reset_data( debug_cpu_ptm0__ETMCIDCMR, val_debug_cpu_ptm0__ETMCIDCMR);
set_reset_data( debug_cpu_ptm0__ETMSYNCFR, val_debug_cpu_ptm0__ETMSYNCFR);
set_reset_data( debug_cpu_ptm0__ETMIDR, val_debug_cpu_ptm0__ETMIDR);
set_reset_data( debug_cpu_ptm0__ETMCCER, val_debug_cpu_ptm0__ETMCCER);
set_reset_data( debug_cpu_ptm0__ETMEXTINSELR, val_debug_cpu_ptm0__ETMEXTINSELR);
set_reset_data( debug_cpu_ptm0__ETMAUXCR, val_debug_cpu_ptm0__ETMAUXCR);
set_reset_data( debug_cpu_ptm0__ETMTRACEIDR, val_debug_cpu_ptm0__ETMTRACEIDR);
set_reset_data( debug_cpu_ptm0__OSLSR, val_debug_cpu_ptm0__OSLSR);
set_reset_data( debug_cpu_ptm0__ETMPDSR, val_debug_cpu_ptm0__ETMPDSR);
set_reset_data( debug_cpu_ptm0__ITMISCOUT, val_debug_cpu_ptm0__ITMISCOUT);
set_reset_data( debug_cpu_ptm0__ITMISCIN, val_debug_cpu_ptm0__ITMISCIN);
set_reset_data( debug_cpu_ptm0__ITTRIGGER, val_debug_cpu_ptm0__ITTRIGGER);
set_reset_data( debug_cpu_ptm0__ITATBDATA0, val_debug_cpu_ptm0__ITATBDATA0);
set_reset_data( debug_cpu_ptm0__ITATBCTR2, val_debug_cpu_ptm0__ITATBCTR2);
set_reset_data( debug_cpu_ptm0__ITATBID, val_debug_cpu_ptm0__ITATBID);
set_reset_data( debug_cpu_ptm0__ITATBCTR0, val_debug_cpu_ptm0__ITATBCTR0);
set_reset_data( debug_cpu_ptm0__ETMITCTRL, val_debug_cpu_ptm0__ETMITCTRL);
set_reset_data( debug_cpu_ptm0__CTSR, val_debug_cpu_ptm0__CTSR);
set_reset_data( debug_cpu_ptm0__CTCR, val_debug_cpu_ptm0__CTCR);
set_reset_data( debug_cpu_ptm0__LAR, val_debug_cpu_ptm0__LAR);
set_reset_data( debug_cpu_ptm0__LSR, val_debug_cpu_ptm0__LSR);
set_reset_data( debug_cpu_ptm0__ASR, val_debug_cpu_ptm0__ASR);
set_reset_data( debug_cpu_ptm0__DEVID, val_debug_cpu_ptm0__DEVID);
set_reset_data( debug_cpu_ptm0__DTIR, val_debug_cpu_ptm0__DTIR);
set_reset_data( debug_cpu_ptm0__PERIPHID4, val_debug_cpu_ptm0__PERIPHID4);
set_reset_data( debug_cpu_ptm0__PERIPHID5, val_debug_cpu_ptm0__PERIPHID5);
set_reset_data( debug_cpu_ptm0__PERIPHID6, val_debug_cpu_ptm0__PERIPHID6);
set_reset_data( debug_cpu_ptm0__PERIPHID7, val_debug_cpu_ptm0__PERIPHID7);
set_reset_data( debug_cpu_ptm0__PERIPHID0, val_debug_cpu_ptm0__PERIPHID0);
set_reset_data( debug_cpu_ptm0__PERIPHID1, val_debug_cpu_ptm0__PERIPHID1);
set_reset_data( debug_cpu_ptm0__PERIPHID2, val_debug_cpu_ptm0__PERIPHID2);
set_reset_data( debug_cpu_ptm0__PERIPHID3, val_debug_cpu_ptm0__PERIPHID3);
set_reset_data( debug_cpu_ptm0__COMPID0, val_debug_cpu_ptm0__COMPID0);
set_reset_data( debug_cpu_ptm0__COMPID1, val_debug_cpu_ptm0__COMPID1);
set_reset_data( debug_cpu_ptm0__COMPID2, val_debug_cpu_ptm0__COMPID2);
set_reset_data( debug_cpu_ptm0__COMPID3, val_debug_cpu_ptm0__COMPID3);

// ************************************************************
//   Module debug_cpu_ptm1 ptm
//   doc version: 
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( debug_cpu_ptm1__ETMCR, val_debug_cpu_ptm1__ETMCR);
set_reset_data( debug_cpu_ptm1__ETMCCR, val_debug_cpu_ptm1__ETMCCR);
set_reset_data( debug_cpu_ptm1__ETMTRIGGER, val_debug_cpu_ptm1__ETMTRIGGER);
set_reset_data( debug_cpu_ptm1__ETMSR, val_debug_cpu_ptm1__ETMSR);
set_reset_data( debug_cpu_ptm1__ETMSCR, val_debug_cpu_ptm1__ETMSCR);
set_reset_data( debug_cpu_ptm1__ETMTSSCR, val_debug_cpu_ptm1__ETMTSSCR);
set_reset_data( debug_cpu_ptm1__ETMTECR1, val_debug_cpu_ptm1__ETMTECR1);
set_reset_data( debug_cpu_ptm1__ETMACVR1, val_debug_cpu_ptm1__ETMACVR1);
set_reset_data( debug_cpu_ptm1__ETMACVR2, val_debug_cpu_ptm1__ETMACVR2);
set_reset_data( debug_cpu_ptm1__ETMACVR3, val_debug_cpu_ptm1__ETMACVR3);
set_reset_data( debug_cpu_ptm1__ETMACVR4, val_debug_cpu_ptm1__ETMACVR4);
set_reset_data( debug_cpu_ptm1__ETMACVR5, val_debug_cpu_ptm1__ETMACVR5);
set_reset_data( debug_cpu_ptm1__ETMACVR6, val_debug_cpu_ptm1__ETMACVR6);
set_reset_data( debug_cpu_ptm1__ETMACVR7, val_debug_cpu_ptm1__ETMACVR7);
set_reset_data( debug_cpu_ptm1__ETMACVR8, val_debug_cpu_ptm1__ETMACVR8);
set_reset_data( debug_cpu_ptm1__ETMACTR1, val_debug_cpu_ptm1__ETMACTR1);
set_reset_data( debug_cpu_ptm1__ETMACTR2, val_debug_cpu_ptm1__ETMACTR2);
set_reset_data( debug_cpu_ptm1__ETMACTR3, val_debug_cpu_ptm1__ETMACTR3);
set_reset_data( debug_cpu_ptm1__ETMACTR4, val_debug_cpu_ptm1__ETMACTR4);
set_reset_data( debug_cpu_ptm1__ETMACTR5, val_debug_cpu_ptm1__ETMACTR5);
set_reset_data( debug_cpu_ptm1__ETMACTR6, val_debug_cpu_ptm1__ETMACTR6);
set_reset_data( debug_cpu_ptm1__ETMACTR7, val_debug_cpu_ptm1__ETMACTR7);
set_reset_data( debug_cpu_ptm1__ETMACTR8, val_debug_cpu_ptm1__ETMACTR8);
set_reset_data( debug_cpu_ptm1__ETMCNTRLDVR1, val_debug_cpu_ptm1__ETMCNTRLDVR1);
set_reset_data( debug_cpu_ptm1__ETMCNTRLDVR2, val_debug_cpu_ptm1__ETMCNTRLDVR2);
set_reset_data( debug_cpu_ptm1__ETMCNTENR1, val_debug_cpu_ptm1__ETMCNTENR1);
set_reset_data( debug_cpu_ptm1__ETMCNTENR2, val_debug_cpu_ptm1__ETMCNTENR2);
set_reset_data( debug_cpu_ptm1__ETMCNTRLDEVR1, val_debug_cpu_ptm1__ETMCNTRLDEVR1);
set_reset_data( debug_cpu_ptm1__ETMCNTRLDEVR2, val_debug_cpu_ptm1__ETMCNTRLDEVR2);
set_reset_data( debug_cpu_ptm1__ETMCNTVR1, val_debug_cpu_ptm1__ETMCNTVR1);
set_reset_data( debug_cpu_ptm1__ETMCNTVR2, val_debug_cpu_ptm1__ETMCNTVR2);
set_reset_data( debug_cpu_ptm1__ETMSQ12EVR, val_debug_cpu_ptm1__ETMSQ12EVR);
set_reset_data( debug_cpu_ptm1__ETMSQ21EVR, val_debug_cpu_ptm1__ETMSQ21EVR);
set_reset_data( debug_cpu_ptm1__ETMSQ23EVR, val_debug_cpu_ptm1__ETMSQ23EVR);
set_reset_data( debug_cpu_ptm1__ETMSQ31EVR, val_debug_cpu_ptm1__ETMSQ31EVR);
set_reset_data( debug_cpu_ptm1__ETMSQ32EVR, val_debug_cpu_ptm1__ETMSQ32EVR);
set_reset_data( debug_cpu_ptm1__ETMSQ13EVR, val_debug_cpu_ptm1__ETMSQ13EVR);
set_reset_data( debug_cpu_ptm1__ETMSQR, val_debug_cpu_ptm1__ETMSQR);
set_reset_data( debug_cpu_ptm1__ETMEXTOUTEVR1, val_debug_cpu_ptm1__ETMEXTOUTEVR1);
set_reset_data( debug_cpu_ptm1__ETMEXTOUTEVR2, val_debug_cpu_ptm1__ETMEXTOUTEVR2);
set_reset_data( debug_cpu_ptm1__ETMCIDCVR1, val_debug_cpu_ptm1__ETMCIDCVR1);
set_reset_data( debug_cpu_ptm1__ETMCIDCMR, val_debug_cpu_ptm1__ETMCIDCMR);
set_reset_data( debug_cpu_ptm1__ETMSYNCFR, val_debug_cpu_ptm1__ETMSYNCFR);
set_reset_data( debug_cpu_ptm1__ETMIDR, val_debug_cpu_ptm1__ETMIDR);
set_reset_data( debug_cpu_ptm1__ETMCCER, val_debug_cpu_ptm1__ETMCCER);
set_reset_data( debug_cpu_ptm1__ETMEXTINSELR, val_debug_cpu_ptm1__ETMEXTINSELR);
set_reset_data( debug_cpu_ptm1__ETMAUXCR, val_debug_cpu_ptm1__ETMAUXCR);
set_reset_data( debug_cpu_ptm1__ETMTRACEIDR, val_debug_cpu_ptm1__ETMTRACEIDR);
set_reset_data( debug_cpu_ptm1__OSLSR, val_debug_cpu_ptm1__OSLSR);
set_reset_data( debug_cpu_ptm1__ETMPDSR, val_debug_cpu_ptm1__ETMPDSR);
set_reset_data( debug_cpu_ptm1__ITMISCOUT, val_debug_cpu_ptm1__ITMISCOUT);
set_reset_data( debug_cpu_ptm1__ITMISCIN, val_debug_cpu_ptm1__ITMISCIN);
set_reset_data( debug_cpu_ptm1__ITTRIGGER, val_debug_cpu_ptm1__ITTRIGGER);
set_reset_data( debug_cpu_ptm1__ITATBDATA0, val_debug_cpu_ptm1__ITATBDATA0);
set_reset_data( debug_cpu_ptm1__ITATBCTR2, val_debug_cpu_ptm1__ITATBCTR2);
set_reset_data( debug_cpu_ptm1__ITATBID, val_debug_cpu_ptm1__ITATBID);
set_reset_data( debug_cpu_ptm1__ITATBCTR0, val_debug_cpu_ptm1__ITATBCTR0);
set_reset_data( debug_cpu_ptm1__ETMITCTRL, val_debug_cpu_ptm1__ETMITCTRL);
set_reset_data( debug_cpu_ptm1__CTSR, val_debug_cpu_ptm1__CTSR);
set_reset_data( debug_cpu_ptm1__CTCR, val_debug_cpu_ptm1__CTCR);
set_reset_data( debug_cpu_ptm1__LAR, val_debug_cpu_ptm1__LAR);
set_reset_data( debug_cpu_ptm1__LSR, val_debug_cpu_ptm1__LSR);
set_reset_data( debug_cpu_ptm1__ASR, val_debug_cpu_ptm1__ASR);
set_reset_data( debug_cpu_ptm1__DEVID, val_debug_cpu_ptm1__DEVID);
set_reset_data( debug_cpu_ptm1__DTIR, val_debug_cpu_ptm1__DTIR);
set_reset_data( debug_cpu_ptm1__PERIPHID4, val_debug_cpu_ptm1__PERIPHID4);
set_reset_data( debug_cpu_ptm1__PERIPHID5, val_debug_cpu_ptm1__PERIPHID5);
set_reset_data( debug_cpu_ptm1__PERIPHID6, val_debug_cpu_ptm1__PERIPHID6);
set_reset_data( debug_cpu_ptm1__PERIPHID7, val_debug_cpu_ptm1__PERIPHID7);
set_reset_data( debug_cpu_ptm1__PERIPHID0, val_debug_cpu_ptm1__PERIPHID0);
set_reset_data( debug_cpu_ptm1__PERIPHID1, val_debug_cpu_ptm1__PERIPHID1);
set_reset_data( debug_cpu_ptm1__PERIPHID2, val_debug_cpu_ptm1__PERIPHID2);
set_reset_data( debug_cpu_ptm1__PERIPHID3, val_debug_cpu_ptm1__PERIPHID3);
set_reset_data( debug_cpu_ptm1__COMPID0, val_debug_cpu_ptm1__COMPID0);
set_reset_data( debug_cpu_ptm1__COMPID1, val_debug_cpu_ptm1__COMPID1);
set_reset_data( debug_cpu_ptm1__COMPID2, val_debug_cpu_ptm1__COMPID2);
set_reset_data( debug_cpu_ptm1__COMPID3, val_debug_cpu_ptm1__COMPID3);

// ************************************************************
//   Module debug_cti_axim cti
//   doc version: 
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( debug_cti_axim__CTICONTROL, val_debug_cti_axim__CTICONTROL);
set_reset_data( debug_cti_axim__CTIINTACK, val_debug_cti_axim__CTIINTACK);
set_reset_data( debug_cti_axim__CTIAPPSET, val_debug_cti_axim__CTIAPPSET);
set_reset_data( debug_cti_axim__CTIAPPCLEAR, val_debug_cti_axim__CTIAPPCLEAR);
set_reset_data( debug_cti_axim__CTIAPPPULSE, val_debug_cti_axim__CTIAPPPULSE);
set_reset_data( debug_cti_axim__CTIINEN0, val_debug_cti_axim__CTIINEN0);
set_reset_data( debug_cti_axim__CTIINEN1, val_debug_cti_axim__CTIINEN1);
set_reset_data( debug_cti_axim__CTIINEN2, val_debug_cti_axim__CTIINEN2);
set_reset_data( debug_cti_axim__CTIINEN3, val_debug_cti_axim__CTIINEN3);
set_reset_data( debug_cti_axim__CTIINEN4, val_debug_cti_axim__CTIINEN4);
set_reset_data( debug_cti_axim__CTIINEN5, val_debug_cti_axim__CTIINEN5);
set_reset_data( debug_cti_axim__CTIINEN6, val_debug_cti_axim__CTIINEN6);
set_reset_data( debug_cti_axim__CTIINEN7, val_debug_cti_axim__CTIINEN7);
set_reset_data( debug_cti_axim__CTIOUTEN0, val_debug_cti_axim__CTIOUTEN0);
set_reset_data( debug_cti_axim__CTIOUTEN1, val_debug_cti_axim__CTIOUTEN1);
set_reset_data( debug_cti_axim__CTIOUTEN2, val_debug_cti_axim__CTIOUTEN2);
set_reset_data( debug_cti_axim__CTIOUTEN3, val_debug_cti_axim__CTIOUTEN3);
set_reset_data( debug_cti_axim__CTIOUTEN4, val_debug_cti_axim__CTIOUTEN4);
set_reset_data( debug_cti_axim__CTIOUTEN5, val_debug_cti_axim__CTIOUTEN5);
set_reset_data( debug_cti_axim__CTIOUTEN6, val_debug_cti_axim__CTIOUTEN6);
set_reset_data( debug_cti_axim__CTIOUTEN7, val_debug_cti_axim__CTIOUTEN7);
set_reset_data( debug_cti_axim__CTITRIGINSTATUS, val_debug_cti_axim__CTITRIGINSTATUS);
set_reset_data( debug_cti_axim__CTITRIGOUTSTATUS, val_debug_cti_axim__CTITRIGOUTSTATUS);
set_reset_data( debug_cti_axim__CTICHINSTATUS, val_debug_cti_axim__CTICHINSTATUS);
set_reset_data( debug_cti_axim__CTICHOUTSTATUS, val_debug_cti_axim__CTICHOUTSTATUS);
set_reset_data( debug_cti_axim__CTIGATE, val_debug_cti_axim__CTIGATE);
set_reset_data( debug_cti_axim__ASICCTL, val_debug_cti_axim__ASICCTL);
set_reset_data( debug_cti_axim__ITCHINACK, val_debug_cti_axim__ITCHINACK);
set_reset_data( debug_cti_axim__ITTRIGINACK, val_debug_cti_axim__ITTRIGINACK);
set_reset_data( debug_cti_axim__ITCHOUT, val_debug_cti_axim__ITCHOUT);
set_reset_data( debug_cti_axim__ITTRIGOUT, val_debug_cti_axim__ITTRIGOUT);
set_reset_data( debug_cti_axim__ITCHOUTACK, val_debug_cti_axim__ITCHOUTACK);
set_reset_data( debug_cti_axim__ITTRIGOUTACK, val_debug_cti_axim__ITTRIGOUTACK);
set_reset_data( debug_cti_axim__ITCHIN, val_debug_cti_axim__ITCHIN);
set_reset_data( debug_cti_axim__ITTRIGIN, val_debug_cti_axim__ITTRIGIN);
set_reset_data( debug_cti_axim__ITCTRL, val_debug_cti_axim__ITCTRL);
set_reset_data( debug_cti_axim__CTSR, val_debug_cti_axim__CTSR);
set_reset_data( debug_cti_axim__CTCR, val_debug_cti_axim__CTCR);
set_reset_data( debug_cti_axim__LAR, val_debug_cti_axim__LAR);
set_reset_data( debug_cti_axim__LSR, val_debug_cti_axim__LSR);
set_reset_data( debug_cti_axim__ASR, val_debug_cti_axim__ASR);
set_reset_data( debug_cti_axim__DEVID, val_debug_cti_axim__DEVID);
set_reset_data( debug_cti_axim__DTIR, val_debug_cti_axim__DTIR);
set_reset_data( debug_cti_axim__PERIPHID4, val_debug_cti_axim__PERIPHID4);
set_reset_data( debug_cti_axim__PERIPHID5, val_debug_cti_axim__PERIPHID5);
set_reset_data( debug_cti_axim__PERIPHID6, val_debug_cti_axim__PERIPHID6);
set_reset_data( debug_cti_axim__PERIPHID7, val_debug_cti_axim__PERIPHID7);
set_reset_data( debug_cti_axim__PERIPHID0, val_debug_cti_axim__PERIPHID0);
set_reset_data( debug_cti_axim__PERIPHID1, val_debug_cti_axim__PERIPHID1);
set_reset_data( debug_cti_axim__PERIPHID2, val_debug_cti_axim__PERIPHID2);
set_reset_data( debug_cti_axim__PERIPHID3, val_debug_cti_axim__PERIPHID3);
set_reset_data( debug_cti_axim__COMPID0, val_debug_cti_axim__COMPID0);
set_reset_data( debug_cti_axim__COMPID1, val_debug_cti_axim__COMPID1);
set_reset_data( debug_cti_axim__COMPID2, val_debug_cti_axim__COMPID2);
set_reset_data( debug_cti_axim__COMPID3, val_debug_cti_axim__COMPID3);

// ************************************************************
//   Module debug_cti_etb_tpiu cti
//   doc version: 
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( debug_cti_etb_tpiu__CTICONTROL, val_debug_cti_etb_tpiu__CTICONTROL);
set_reset_data( debug_cti_etb_tpiu__CTIINTACK, val_debug_cti_etb_tpiu__CTIINTACK);
set_reset_data( debug_cti_etb_tpiu__CTIAPPSET, val_debug_cti_etb_tpiu__CTIAPPSET);
set_reset_data( debug_cti_etb_tpiu__CTIAPPCLEAR, val_debug_cti_etb_tpiu__CTIAPPCLEAR);
set_reset_data( debug_cti_etb_tpiu__CTIAPPPULSE, val_debug_cti_etb_tpiu__CTIAPPPULSE);
set_reset_data( debug_cti_etb_tpiu__CTIINEN0, val_debug_cti_etb_tpiu__CTIINEN0);
set_reset_data( debug_cti_etb_tpiu__CTIINEN1, val_debug_cti_etb_tpiu__CTIINEN1);
set_reset_data( debug_cti_etb_tpiu__CTIINEN2, val_debug_cti_etb_tpiu__CTIINEN2);
set_reset_data( debug_cti_etb_tpiu__CTIINEN3, val_debug_cti_etb_tpiu__CTIINEN3);
set_reset_data( debug_cti_etb_tpiu__CTIINEN4, val_debug_cti_etb_tpiu__CTIINEN4);
set_reset_data( debug_cti_etb_tpiu__CTIINEN5, val_debug_cti_etb_tpiu__CTIINEN5);
set_reset_data( debug_cti_etb_tpiu__CTIINEN6, val_debug_cti_etb_tpiu__CTIINEN6);
set_reset_data( debug_cti_etb_tpiu__CTIINEN7, val_debug_cti_etb_tpiu__CTIINEN7);
set_reset_data( debug_cti_etb_tpiu__CTIOUTEN0, val_debug_cti_etb_tpiu__CTIOUTEN0);
set_reset_data( debug_cti_etb_tpiu__CTIOUTEN1, val_debug_cti_etb_tpiu__CTIOUTEN1);
set_reset_data( debug_cti_etb_tpiu__CTIOUTEN2, val_debug_cti_etb_tpiu__CTIOUTEN2);
set_reset_data( debug_cti_etb_tpiu__CTIOUTEN3, val_debug_cti_etb_tpiu__CTIOUTEN3);
set_reset_data( debug_cti_etb_tpiu__CTIOUTEN4, val_debug_cti_etb_tpiu__CTIOUTEN4);
set_reset_data( debug_cti_etb_tpiu__CTIOUTEN5, val_debug_cti_etb_tpiu__CTIOUTEN5);
set_reset_data( debug_cti_etb_tpiu__CTIOUTEN6, val_debug_cti_etb_tpiu__CTIOUTEN6);
set_reset_data( debug_cti_etb_tpiu__CTIOUTEN7, val_debug_cti_etb_tpiu__CTIOUTEN7);
set_reset_data( debug_cti_etb_tpiu__CTITRIGINSTATUS, val_debug_cti_etb_tpiu__CTITRIGINSTATUS);
set_reset_data( debug_cti_etb_tpiu__CTITRIGOUTSTATUS, val_debug_cti_etb_tpiu__CTITRIGOUTSTATUS);
set_reset_data( debug_cti_etb_tpiu__CTICHINSTATUS, val_debug_cti_etb_tpiu__CTICHINSTATUS);
set_reset_data( debug_cti_etb_tpiu__CTICHOUTSTATUS, val_debug_cti_etb_tpiu__CTICHOUTSTATUS);
set_reset_data( debug_cti_etb_tpiu__CTIGATE, val_debug_cti_etb_tpiu__CTIGATE);
set_reset_data( debug_cti_etb_tpiu__ASICCTL, val_debug_cti_etb_tpiu__ASICCTL);
set_reset_data( debug_cti_etb_tpiu__ITCHINACK, val_debug_cti_etb_tpiu__ITCHINACK);
set_reset_data( debug_cti_etb_tpiu__ITTRIGINACK, val_debug_cti_etb_tpiu__ITTRIGINACK);
set_reset_data( debug_cti_etb_tpiu__ITCHOUT, val_debug_cti_etb_tpiu__ITCHOUT);
set_reset_data( debug_cti_etb_tpiu__ITTRIGOUT, val_debug_cti_etb_tpiu__ITTRIGOUT);
set_reset_data( debug_cti_etb_tpiu__ITCHOUTACK, val_debug_cti_etb_tpiu__ITCHOUTACK);
set_reset_data( debug_cti_etb_tpiu__ITTRIGOUTACK, val_debug_cti_etb_tpiu__ITTRIGOUTACK);
set_reset_data( debug_cti_etb_tpiu__ITCHIN, val_debug_cti_etb_tpiu__ITCHIN);
set_reset_data( debug_cti_etb_tpiu__ITTRIGIN, val_debug_cti_etb_tpiu__ITTRIGIN);
set_reset_data( debug_cti_etb_tpiu__ITCTRL, val_debug_cti_etb_tpiu__ITCTRL);
set_reset_data( debug_cti_etb_tpiu__CTSR, val_debug_cti_etb_tpiu__CTSR);
set_reset_data( debug_cti_etb_tpiu__CTCR, val_debug_cti_etb_tpiu__CTCR);
set_reset_data( debug_cti_etb_tpiu__LAR, val_debug_cti_etb_tpiu__LAR);
set_reset_data( debug_cti_etb_tpiu__LSR, val_debug_cti_etb_tpiu__LSR);
set_reset_data( debug_cti_etb_tpiu__ASR, val_debug_cti_etb_tpiu__ASR);
set_reset_data( debug_cti_etb_tpiu__DEVID, val_debug_cti_etb_tpiu__DEVID);
set_reset_data( debug_cti_etb_tpiu__DTIR, val_debug_cti_etb_tpiu__DTIR);
set_reset_data( debug_cti_etb_tpiu__PERIPHID4, val_debug_cti_etb_tpiu__PERIPHID4);
set_reset_data( debug_cti_etb_tpiu__PERIPHID5, val_debug_cti_etb_tpiu__PERIPHID5);
set_reset_data( debug_cti_etb_tpiu__PERIPHID6, val_debug_cti_etb_tpiu__PERIPHID6);
set_reset_data( debug_cti_etb_tpiu__PERIPHID7, val_debug_cti_etb_tpiu__PERIPHID7);
set_reset_data( debug_cti_etb_tpiu__PERIPHID0, val_debug_cti_etb_tpiu__PERIPHID0);
set_reset_data( debug_cti_etb_tpiu__PERIPHID1, val_debug_cti_etb_tpiu__PERIPHID1);
set_reset_data( debug_cti_etb_tpiu__PERIPHID2, val_debug_cti_etb_tpiu__PERIPHID2);
set_reset_data( debug_cti_etb_tpiu__PERIPHID3, val_debug_cti_etb_tpiu__PERIPHID3);
set_reset_data( debug_cti_etb_tpiu__COMPID0, val_debug_cti_etb_tpiu__COMPID0);
set_reset_data( debug_cti_etb_tpiu__COMPID1, val_debug_cti_etb_tpiu__COMPID1);
set_reset_data( debug_cti_etb_tpiu__COMPID2, val_debug_cti_etb_tpiu__COMPID2);
set_reset_data( debug_cti_etb_tpiu__COMPID3, val_debug_cti_etb_tpiu__COMPID3);

// ************************************************************
//   Module debug_cti_ftm cti
//   doc version: 
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( debug_cti_ftm__CTICONTROL, val_debug_cti_ftm__CTICONTROL);
set_reset_data( debug_cti_ftm__CTIINTACK, val_debug_cti_ftm__CTIINTACK);
set_reset_data( debug_cti_ftm__CTIAPPSET, val_debug_cti_ftm__CTIAPPSET);
set_reset_data( debug_cti_ftm__CTIAPPCLEAR, val_debug_cti_ftm__CTIAPPCLEAR);
set_reset_data( debug_cti_ftm__CTIAPPPULSE, val_debug_cti_ftm__CTIAPPPULSE);
set_reset_data( debug_cti_ftm__CTIINEN0, val_debug_cti_ftm__CTIINEN0);
set_reset_data( debug_cti_ftm__CTIINEN1, val_debug_cti_ftm__CTIINEN1);
set_reset_data( debug_cti_ftm__CTIINEN2, val_debug_cti_ftm__CTIINEN2);
set_reset_data( debug_cti_ftm__CTIINEN3, val_debug_cti_ftm__CTIINEN3);
set_reset_data( debug_cti_ftm__CTIINEN4, val_debug_cti_ftm__CTIINEN4);
set_reset_data( debug_cti_ftm__CTIINEN5, val_debug_cti_ftm__CTIINEN5);
set_reset_data( debug_cti_ftm__CTIINEN6, val_debug_cti_ftm__CTIINEN6);
set_reset_data( debug_cti_ftm__CTIINEN7, val_debug_cti_ftm__CTIINEN7);
set_reset_data( debug_cti_ftm__CTIOUTEN0, val_debug_cti_ftm__CTIOUTEN0);
set_reset_data( debug_cti_ftm__CTIOUTEN1, val_debug_cti_ftm__CTIOUTEN1);
set_reset_data( debug_cti_ftm__CTIOUTEN2, val_debug_cti_ftm__CTIOUTEN2);
set_reset_data( debug_cti_ftm__CTIOUTEN3, val_debug_cti_ftm__CTIOUTEN3);
set_reset_data( debug_cti_ftm__CTIOUTEN4, val_debug_cti_ftm__CTIOUTEN4);
set_reset_data( debug_cti_ftm__CTIOUTEN5, val_debug_cti_ftm__CTIOUTEN5);
set_reset_data( debug_cti_ftm__CTIOUTEN6, val_debug_cti_ftm__CTIOUTEN6);
set_reset_data( debug_cti_ftm__CTIOUTEN7, val_debug_cti_ftm__CTIOUTEN7);
set_reset_data( debug_cti_ftm__CTITRIGINSTATUS, val_debug_cti_ftm__CTITRIGINSTATUS);
set_reset_data( debug_cti_ftm__CTITRIGOUTSTATUS, val_debug_cti_ftm__CTITRIGOUTSTATUS);
set_reset_data( debug_cti_ftm__CTICHINSTATUS, val_debug_cti_ftm__CTICHINSTATUS);
set_reset_data( debug_cti_ftm__CTICHOUTSTATUS, val_debug_cti_ftm__CTICHOUTSTATUS);
set_reset_data( debug_cti_ftm__CTIGATE, val_debug_cti_ftm__CTIGATE);
set_reset_data( debug_cti_ftm__ASICCTL, val_debug_cti_ftm__ASICCTL);
set_reset_data( debug_cti_ftm__ITCHINACK, val_debug_cti_ftm__ITCHINACK);
set_reset_data( debug_cti_ftm__ITTRIGINACK, val_debug_cti_ftm__ITTRIGINACK);
set_reset_data( debug_cti_ftm__ITCHOUT, val_debug_cti_ftm__ITCHOUT);
set_reset_data( debug_cti_ftm__ITTRIGOUT, val_debug_cti_ftm__ITTRIGOUT);
set_reset_data( debug_cti_ftm__ITCHOUTACK, val_debug_cti_ftm__ITCHOUTACK);
set_reset_data( debug_cti_ftm__ITTRIGOUTACK, val_debug_cti_ftm__ITTRIGOUTACK);
set_reset_data( debug_cti_ftm__ITCHIN, val_debug_cti_ftm__ITCHIN);
set_reset_data( debug_cti_ftm__ITTRIGIN, val_debug_cti_ftm__ITTRIGIN);
set_reset_data( debug_cti_ftm__ITCTRL, val_debug_cti_ftm__ITCTRL);
set_reset_data( debug_cti_ftm__CTSR, val_debug_cti_ftm__CTSR);
set_reset_data( debug_cti_ftm__CTCR, val_debug_cti_ftm__CTCR);
set_reset_data( debug_cti_ftm__LAR, val_debug_cti_ftm__LAR);
set_reset_data( debug_cti_ftm__LSR, val_debug_cti_ftm__LSR);
set_reset_data( debug_cti_ftm__ASR, val_debug_cti_ftm__ASR);
set_reset_data( debug_cti_ftm__DEVID, val_debug_cti_ftm__DEVID);
set_reset_data( debug_cti_ftm__DTIR, val_debug_cti_ftm__DTIR);
set_reset_data( debug_cti_ftm__PERIPHID4, val_debug_cti_ftm__PERIPHID4);
set_reset_data( debug_cti_ftm__PERIPHID5, val_debug_cti_ftm__PERIPHID5);
set_reset_data( debug_cti_ftm__PERIPHID6, val_debug_cti_ftm__PERIPHID6);
set_reset_data( debug_cti_ftm__PERIPHID7, val_debug_cti_ftm__PERIPHID7);
set_reset_data( debug_cti_ftm__PERIPHID0, val_debug_cti_ftm__PERIPHID0);
set_reset_data( debug_cti_ftm__PERIPHID1, val_debug_cti_ftm__PERIPHID1);
set_reset_data( debug_cti_ftm__PERIPHID2, val_debug_cti_ftm__PERIPHID2);
set_reset_data( debug_cti_ftm__PERIPHID3, val_debug_cti_ftm__PERIPHID3);
set_reset_data( debug_cti_ftm__COMPID0, val_debug_cti_ftm__COMPID0);
set_reset_data( debug_cti_ftm__COMPID1, val_debug_cti_ftm__COMPID1);
set_reset_data( debug_cti_ftm__COMPID2, val_debug_cti_ftm__COMPID2);
set_reset_data( debug_cti_ftm__COMPID3, val_debug_cti_ftm__COMPID3);

// ************************************************************
//   Module debug_dap_rom dap
//   doc version: 
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( debug_dap_rom__ROMENTRY00, val_debug_dap_rom__ROMENTRY00);
set_reset_data( debug_dap_rom__ROMENTRY01, val_debug_dap_rom__ROMENTRY01);
set_reset_data( debug_dap_rom__ROMENTRY02, val_debug_dap_rom__ROMENTRY02);
set_reset_data( debug_dap_rom__ROMENTRY03, val_debug_dap_rom__ROMENTRY03);
set_reset_data( debug_dap_rom__ROMENTRY04, val_debug_dap_rom__ROMENTRY04);
set_reset_data( debug_dap_rom__ROMENTRY05, val_debug_dap_rom__ROMENTRY05);
set_reset_data( debug_dap_rom__ROMENTRY06, val_debug_dap_rom__ROMENTRY06);
set_reset_data( debug_dap_rom__ROMENTRY07, val_debug_dap_rom__ROMENTRY07);
set_reset_data( debug_dap_rom__ROMENTRY08, val_debug_dap_rom__ROMENTRY08);
set_reset_data( debug_dap_rom__ROMENTRY09, val_debug_dap_rom__ROMENTRY09);
set_reset_data( debug_dap_rom__ROMENTRY10, val_debug_dap_rom__ROMENTRY10);
set_reset_data( debug_dap_rom__ROMENTRY11, val_debug_dap_rom__ROMENTRY11);
set_reset_data( debug_dap_rom__ROMENTRY12, val_debug_dap_rom__ROMENTRY12);
set_reset_data( debug_dap_rom__ROMENTRY13, val_debug_dap_rom__ROMENTRY13);
set_reset_data( debug_dap_rom__ROMENTRY14, val_debug_dap_rom__ROMENTRY14);
set_reset_data( debug_dap_rom__ROMENTRY15, val_debug_dap_rom__ROMENTRY15);
set_reset_data( debug_dap_rom__PERIPHID4, val_debug_dap_rom__PERIPHID4);
set_reset_data( debug_dap_rom__PERIPHID5, val_debug_dap_rom__PERIPHID5);
set_reset_data( debug_dap_rom__PERIPHID6, val_debug_dap_rom__PERIPHID6);
set_reset_data( debug_dap_rom__PERIPHID7, val_debug_dap_rom__PERIPHID7);
set_reset_data( debug_dap_rom__PERIPHID0, val_debug_dap_rom__PERIPHID0);
set_reset_data( debug_dap_rom__PERIPHID1, val_debug_dap_rom__PERIPHID1);
set_reset_data( debug_dap_rom__PERIPHID2, val_debug_dap_rom__PERIPHID2);
set_reset_data( debug_dap_rom__PERIPHID3, val_debug_dap_rom__PERIPHID3);
set_reset_data( debug_dap_rom__COMPID0, val_debug_dap_rom__COMPID0);
set_reset_data( debug_dap_rom__COMPID1, val_debug_dap_rom__COMPID1);
set_reset_data( debug_dap_rom__COMPID2, val_debug_dap_rom__COMPID2);
set_reset_data( debug_dap_rom__COMPID3, val_debug_dap_rom__COMPID3);

// ************************************************************
//   Module debug_etb etb
//   doc version: 
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( debug_etb__RDP, val_debug_etb__RDP);
set_reset_data( debug_etb__STS, val_debug_etb__STS);
set_reset_data( debug_etb__RRD, val_debug_etb__RRD);
set_reset_data( debug_etb__RRP, val_debug_etb__RRP);
set_reset_data( debug_etb__RWP, val_debug_etb__RWP);
set_reset_data( debug_etb__TRG, val_debug_etb__TRG);
set_reset_data( debug_etb__CTL, val_debug_etb__CTL);
set_reset_data( debug_etb__RWD, val_debug_etb__RWD);
set_reset_data( debug_etb__FFSR, val_debug_etb__FFSR);
set_reset_data( debug_etb__FFCR, val_debug_etb__FFCR);
set_reset_data( debug_etb__ITMISCOP0, val_debug_etb__ITMISCOP0);
set_reset_data( debug_etb__ITTRFLINACK, val_debug_etb__ITTRFLINACK);
set_reset_data( debug_etb__ITTRFLIN, val_debug_etb__ITTRFLIN);
set_reset_data( debug_etb__ITATBDATA0, val_debug_etb__ITATBDATA0);
set_reset_data( debug_etb__ITATBCTR2, val_debug_etb__ITATBCTR2);
set_reset_data( debug_etb__ITATBCTR1, val_debug_etb__ITATBCTR1);
set_reset_data( debug_etb__ITATBCTR0, val_debug_etb__ITATBCTR0);
set_reset_data( debug_etb__IMCR, val_debug_etb__IMCR);
set_reset_data( debug_etb__CTSR, val_debug_etb__CTSR);
set_reset_data( debug_etb__CTCR, val_debug_etb__CTCR);
set_reset_data( debug_etb__LAR, val_debug_etb__LAR);
set_reset_data( debug_etb__LSR, val_debug_etb__LSR);
set_reset_data( debug_etb__ASR, val_debug_etb__ASR);
set_reset_data( debug_etb__DEVID, val_debug_etb__DEVID);
set_reset_data( debug_etb__DTIR, val_debug_etb__DTIR);
set_reset_data( debug_etb__PERIPHID4, val_debug_etb__PERIPHID4);
set_reset_data( debug_etb__PERIPHID5, val_debug_etb__PERIPHID5);
set_reset_data( debug_etb__PERIPHID6, val_debug_etb__PERIPHID6);
set_reset_data( debug_etb__PERIPHID7, val_debug_etb__PERIPHID7);
set_reset_data( debug_etb__PERIPHID0, val_debug_etb__PERIPHID0);
set_reset_data( debug_etb__PERIPHID1, val_debug_etb__PERIPHID1);
set_reset_data( debug_etb__PERIPHID2, val_debug_etb__PERIPHID2);
set_reset_data( debug_etb__PERIPHID3, val_debug_etb__PERIPHID3);
set_reset_data( debug_etb__COMPID0, val_debug_etb__COMPID0);
set_reset_data( debug_etb__COMPID1, val_debug_etb__COMPID1);
set_reset_data( debug_etb__COMPID2, val_debug_etb__COMPID2);
set_reset_data( debug_etb__COMPID3, val_debug_etb__COMPID3);

// ************************************************************
//   Module debug_ftm ftm
//   doc version: 
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( debug_ftm__FTMGLBCTRL, val_debug_ftm__FTMGLBCTRL);
set_reset_data( debug_ftm__FTMSTATUS, val_debug_ftm__FTMSTATUS);
set_reset_data( debug_ftm__FTMCONTROL, val_debug_ftm__FTMCONTROL);
set_reset_data( debug_ftm__FTMP2FDBG0, val_debug_ftm__FTMP2FDBG0);
set_reset_data( debug_ftm__FTMP2FDBG1, val_debug_ftm__FTMP2FDBG1);
set_reset_data( debug_ftm__FTMP2FDBG2, val_debug_ftm__FTMP2FDBG2);
set_reset_data( debug_ftm__FTMP2FDBG3, val_debug_ftm__FTMP2FDBG3);
set_reset_data( debug_ftm__FTMF2PDBG0, val_debug_ftm__FTMF2PDBG0);
set_reset_data( debug_ftm__FTMF2PDBG1, val_debug_ftm__FTMF2PDBG1);
set_reset_data( debug_ftm__FTMF2PDBG2, val_debug_ftm__FTMF2PDBG2);
set_reset_data( debug_ftm__FTMF2PDBG3, val_debug_ftm__FTMF2PDBG3);
set_reset_data( debug_ftm__CYCOUNTPRE, val_debug_ftm__CYCOUNTPRE);
set_reset_data( debug_ftm__FTMSYNCRELOAD, val_debug_ftm__FTMSYNCRELOAD);
set_reset_data( debug_ftm__FTMSYNCCOUT, val_debug_ftm__FTMSYNCCOUT);
set_reset_data( debug_ftm__FTMATID, val_debug_ftm__FTMATID);
set_reset_data( debug_ftm__FTMITTRIGOUTACK, val_debug_ftm__FTMITTRIGOUTACK);
set_reset_data( debug_ftm__FTMITTRIGGER, val_debug_ftm__FTMITTRIGGER);
set_reset_data( debug_ftm__FTMITTRACEDIS, val_debug_ftm__FTMITTRACEDIS);
set_reset_data( debug_ftm__FTMITCYCCOUNT, val_debug_ftm__FTMITCYCCOUNT);
set_reset_data( debug_ftm__FTMITATBDATA0, val_debug_ftm__FTMITATBDATA0);
set_reset_data( debug_ftm__FTMITATBCTR2, val_debug_ftm__FTMITATBCTR2);
set_reset_data( debug_ftm__FTMITATBCTR1, val_debug_ftm__FTMITATBCTR1);
set_reset_data( debug_ftm__FTMITATBCTR0, val_debug_ftm__FTMITATBCTR0);
set_reset_data( debug_ftm__FTMITCR, val_debug_ftm__FTMITCR);
set_reset_data( debug_ftm__CLAIMTAGSET, val_debug_ftm__CLAIMTAGSET);
set_reset_data( debug_ftm__CLAIMTAGCLR, val_debug_ftm__CLAIMTAGCLR);
set_reset_data( debug_ftm__LOCK_ACCESS, val_debug_ftm__LOCK_ACCESS);
set_reset_data( debug_ftm__LOCK_STATUS, val_debug_ftm__LOCK_STATUS);
set_reset_data( debug_ftm__FTMAUTHSTATUS, val_debug_ftm__FTMAUTHSTATUS);
set_reset_data( debug_ftm__FTMDEVID, val_debug_ftm__FTMDEVID);
set_reset_data( debug_ftm__FTMDEV_TYPE, val_debug_ftm__FTMDEV_TYPE);
set_reset_data( debug_ftm__FTMPERIPHID4, val_debug_ftm__FTMPERIPHID4);
set_reset_data( debug_ftm__FTMPERIPHID5, val_debug_ftm__FTMPERIPHID5);
set_reset_data( debug_ftm__FTMPERIPHID6, val_debug_ftm__FTMPERIPHID6);
set_reset_data( debug_ftm__FTMPERIPHID7, val_debug_ftm__FTMPERIPHID7);
set_reset_data( debug_ftm__FTMPERIPHID0, val_debug_ftm__FTMPERIPHID0);
set_reset_data( debug_ftm__FTMPERIPHID1, val_debug_ftm__FTMPERIPHID1);
set_reset_data( debug_ftm__FTMPERIPHID2, val_debug_ftm__FTMPERIPHID2);
set_reset_data( debug_ftm__FTMPERIPHID3, val_debug_ftm__FTMPERIPHID3);
set_reset_data( debug_ftm__FTMCOMPONID0, val_debug_ftm__FTMCOMPONID0);
set_reset_data( debug_ftm__FTMCOMPONID1, val_debug_ftm__FTMCOMPONID1);
set_reset_data( debug_ftm__FTMCOMPONID2, val_debug_ftm__FTMCOMPONID2);
set_reset_data( debug_ftm__FTMCOMPONID3, val_debug_ftm__FTMCOMPONID3);

// ************************************************************
//   Module debug_funnel funnel
//   doc version: 
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( debug_funnel__Control, val_debug_funnel__Control);
set_reset_data( debug_funnel__PriControl, val_debug_funnel__PriControl);
set_reset_data( debug_funnel__ITATBDATA0, val_debug_funnel__ITATBDATA0);
set_reset_data( debug_funnel__ITATBCTR2, val_debug_funnel__ITATBCTR2);
set_reset_data( debug_funnel__ITATBCTR1, val_debug_funnel__ITATBCTR1);
set_reset_data( debug_funnel__ITATBCTR0, val_debug_funnel__ITATBCTR0);
set_reset_data( debug_funnel__IMCR, val_debug_funnel__IMCR);
set_reset_data( debug_funnel__CTSR, val_debug_funnel__CTSR);
set_reset_data( debug_funnel__CTCR, val_debug_funnel__CTCR);
set_reset_data( debug_funnel__LAR, val_debug_funnel__LAR);
set_reset_data( debug_funnel__LSR, val_debug_funnel__LSR);
set_reset_data( debug_funnel__ASR, val_debug_funnel__ASR);
set_reset_data( debug_funnel__DEVID, val_debug_funnel__DEVID);
set_reset_data( debug_funnel__DTIR, val_debug_funnel__DTIR);
set_reset_data( debug_funnel__PERIPHID4, val_debug_funnel__PERIPHID4);
set_reset_data( debug_funnel__PERIPHID5, val_debug_funnel__PERIPHID5);
set_reset_data( debug_funnel__PERIPHID6, val_debug_funnel__PERIPHID6);
set_reset_data( debug_funnel__PERIPHID7, val_debug_funnel__PERIPHID7);
set_reset_data( debug_funnel__PERIPHID0, val_debug_funnel__PERIPHID0);
set_reset_data( debug_funnel__PERIPHID1, val_debug_funnel__PERIPHID1);
set_reset_data( debug_funnel__PERIPHID2, val_debug_funnel__PERIPHID2);
set_reset_data( debug_funnel__PERIPHID3, val_debug_funnel__PERIPHID3);
set_reset_data( debug_funnel__COMPID0, val_debug_funnel__COMPID0);
set_reset_data( debug_funnel__COMPID1, val_debug_funnel__COMPID1);
set_reset_data( debug_funnel__COMPID2, val_debug_funnel__COMPID2);
set_reset_data( debug_funnel__COMPID3, val_debug_funnel__COMPID3);

// ************************************************************
//   Module debug_itm itm
//   doc version: 
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( debug_itm__StimPort00, val_debug_itm__StimPort00);
set_reset_data( debug_itm__StimPort01, val_debug_itm__StimPort01);
set_reset_data( debug_itm__StimPort02, val_debug_itm__StimPort02);
set_reset_data( debug_itm__StimPort03, val_debug_itm__StimPort03);
set_reset_data( debug_itm__StimPort04, val_debug_itm__StimPort04);
set_reset_data( debug_itm__StimPort05, val_debug_itm__StimPort05);
set_reset_data( debug_itm__StimPort06, val_debug_itm__StimPort06);
set_reset_data( debug_itm__StimPort07, val_debug_itm__StimPort07);
set_reset_data( debug_itm__StimPort08, val_debug_itm__StimPort08);
set_reset_data( debug_itm__StimPort09, val_debug_itm__StimPort09);
set_reset_data( debug_itm__StimPort10, val_debug_itm__StimPort10);
set_reset_data( debug_itm__StimPort11, val_debug_itm__StimPort11);
set_reset_data( debug_itm__StimPort12, val_debug_itm__StimPort12);
set_reset_data( debug_itm__StimPort13, val_debug_itm__StimPort13);
set_reset_data( debug_itm__StimPort14, val_debug_itm__StimPort14);
set_reset_data( debug_itm__StimPort15, val_debug_itm__StimPort15);
set_reset_data( debug_itm__StimPort16, val_debug_itm__StimPort16);
set_reset_data( debug_itm__StimPort17, val_debug_itm__StimPort17);
set_reset_data( debug_itm__StimPort18, val_debug_itm__StimPort18);
set_reset_data( debug_itm__StimPort19, val_debug_itm__StimPort19);
set_reset_data( debug_itm__StimPort20, val_debug_itm__StimPort20);
set_reset_data( debug_itm__StimPort21, val_debug_itm__StimPort21);
set_reset_data( debug_itm__StimPort22, val_debug_itm__StimPort22);
set_reset_data( debug_itm__StimPort23, val_debug_itm__StimPort23);
set_reset_data( debug_itm__StimPort24, val_debug_itm__StimPort24);
set_reset_data( debug_itm__StimPort25, val_debug_itm__StimPort25);
set_reset_data( debug_itm__StimPort26, val_debug_itm__StimPort26);
set_reset_data( debug_itm__StimPort27, val_debug_itm__StimPort27);
set_reset_data( debug_itm__StimPort28, val_debug_itm__StimPort28);
set_reset_data( debug_itm__StimPort29, val_debug_itm__StimPort29);
set_reset_data( debug_itm__StimPort30, val_debug_itm__StimPort30);
set_reset_data( debug_itm__StimPort31, val_debug_itm__StimPort31);
set_reset_data( debug_itm__TER, val_debug_itm__TER);
set_reset_data( debug_itm__TTR, val_debug_itm__TTR);
set_reset_data( debug_itm__CR, val_debug_itm__CR);
set_reset_data( debug_itm__SCR, val_debug_itm__SCR);
set_reset_data( debug_itm__ITTRIGOUTACK, val_debug_itm__ITTRIGOUTACK);
set_reset_data( debug_itm__ITTRIGOUT, val_debug_itm__ITTRIGOUT);
set_reset_data( debug_itm__ITATBDATA0, val_debug_itm__ITATBDATA0);
set_reset_data( debug_itm__ITATBCTR2, val_debug_itm__ITATBCTR2);
set_reset_data( debug_itm__ITATABCTR1, val_debug_itm__ITATABCTR1);
set_reset_data( debug_itm__ITATBCTR0, val_debug_itm__ITATBCTR0);
set_reset_data( debug_itm__IMCR, val_debug_itm__IMCR);
set_reset_data( debug_itm__CTSR, val_debug_itm__CTSR);
set_reset_data( debug_itm__CTCR, val_debug_itm__CTCR);
set_reset_data( debug_itm__LAR, val_debug_itm__LAR);
set_reset_data( debug_itm__LSR, val_debug_itm__LSR);
set_reset_data( debug_itm__ASR, val_debug_itm__ASR);
set_reset_data( debug_itm__DEVID, val_debug_itm__DEVID);
set_reset_data( debug_itm__DTIR, val_debug_itm__DTIR);
set_reset_data( debug_itm__PERIPHID4, val_debug_itm__PERIPHID4);
set_reset_data( debug_itm__PERIPHID5, val_debug_itm__PERIPHID5);
set_reset_data( debug_itm__PERIPHID6, val_debug_itm__PERIPHID6);
set_reset_data( debug_itm__PERIPHID7, val_debug_itm__PERIPHID7);
set_reset_data( debug_itm__PERIPHID0, val_debug_itm__PERIPHID0);
set_reset_data( debug_itm__PERIPHID1, val_debug_itm__PERIPHID1);
set_reset_data( debug_itm__PERIPHID2, val_debug_itm__PERIPHID2);
set_reset_data( debug_itm__PERIPHID3, val_debug_itm__PERIPHID3);
set_reset_data( debug_itm__COMPID0, val_debug_itm__COMPID0);
set_reset_data( debug_itm__COMPID1, val_debug_itm__COMPID1);
set_reset_data( debug_itm__COMPID2, val_debug_itm__COMPID2);
set_reset_data( debug_itm__COMPID3, val_debug_itm__COMPID3);

// ************************************************************
//   Module debug_tpiu tpiu
//   doc version: 
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( debug_tpiu__SuppSize, val_debug_tpiu__SuppSize);
set_reset_data( debug_tpiu__CurrentSize, val_debug_tpiu__CurrentSize);
set_reset_data( debug_tpiu__SuppTrigMode, val_debug_tpiu__SuppTrigMode);
set_reset_data( debug_tpiu__TrigCount, val_debug_tpiu__TrigCount);
set_reset_data( debug_tpiu__TrigMult, val_debug_tpiu__TrigMult);
set_reset_data( debug_tpiu__SuppTest, val_debug_tpiu__SuppTest);
set_reset_data( debug_tpiu__CurrentTest, val_debug_tpiu__CurrentTest);
set_reset_data( debug_tpiu__TestRepeatCount, val_debug_tpiu__TestRepeatCount);
set_reset_data( debug_tpiu__FFSR, val_debug_tpiu__FFSR);
set_reset_data( debug_tpiu__FFCR, val_debug_tpiu__FFCR);
set_reset_data( debug_tpiu__FormatSyncCount, val_debug_tpiu__FormatSyncCount);
set_reset_data( debug_tpiu__EXTCTLIn, val_debug_tpiu__EXTCTLIn);
set_reset_data( debug_tpiu__EXTCTLOut, val_debug_tpiu__EXTCTLOut);
set_reset_data( debug_tpiu__ITTRFLINACK, val_debug_tpiu__ITTRFLINACK);
set_reset_data( debug_tpiu__ITTRFLIN, val_debug_tpiu__ITTRFLIN);
set_reset_data( debug_tpiu__ITATBDATA0, val_debug_tpiu__ITATBDATA0);
set_reset_data( debug_tpiu__ITATBCTR2, val_debug_tpiu__ITATBCTR2);
set_reset_data( debug_tpiu__ITATBCTR1, val_debug_tpiu__ITATBCTR1);
set_reset_data( debug_tpiu__ITATBCTR0, val_debug_tpiu__ITATBCTR0);
set_reset_data( debug_tpiu__IMCR, val_debug_tpiu__IMCR);
set_reset_data( debug_tpiu__CTSR, val_debug_tpiu__CTSR);
set_reset_data( debug_tpiu__CTCR, val_debug_tpiu__CTCR);
set_reset_data( debug_tpiu__LAR, val_debug_tpiu__LAR);
set_reset_data( debug_tpiu__LSR, val_debug_tpiu__LSR);
set_reset_data( debug_tpiu__ASR, val_debug_tpiu__ASR);
set_reset_data( debug_tpiu__DEVID, val_debug_tpiu__DEVID);
set_reset_data( debug_tpiu__DTIR, val_debug_tpiu__DTIR);
set_reset_data( debug_tpiu__PERIPHID4, val_debug_tpiu__PERIPHID4);
set_reset_data( debug_tpiu__PERIPHID5, val_debug_tpiu__PERIPHID5);
set_reset_data( debug_tpiu__PERIPHID6, val_debug_tpiu__PERIPHID6);
set_reset_data( debug_tpiu__PERIPHID7, val_debug_tpiu__PERIPHID7);
set_reset_data( debug_tpiu__PERIPHID0, val_debug_tpiu__PERIPHID0);
set_reset_data( debug_tpiu__PERIPHID1, val_debug_tpiu__PERIPHID1);
set_reset_data( debug_tpiu__PERIPHID2, val_debug_tpiu__PERIPHID2);
set_reset_data( debug_tpiu__PERIPHID3, val_debug_tpiu__PERIPHID3);
set_reset_data( debug_tpiu__COMPID0, val_debug_tpiu__COMPID0);
set_reset_data( debug_tpiu__COMPID1, val_debug_tpiu__COMPID1);
set_reset_data( debug_tpiu__COMPID2, val_debug_tpiu__COMPID2);
set_reset_data( debug_tpiu__COMPID3, val_debug_tpiu__COMPID3);

// ************************************************************
//   Module devcfg devcfg
//   doc version: 1.1
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( devcfg__CTRL, val_devcfg__CTRL);
set_reset_data( devcfg__LOCK, val_devcfg__LOCK);
set_reset_data( devcfg__CFG, val_devcfg__CFG);
set_reset_data( devcfg__INT_STS, val_devcfg__INT_STS);
set_reset_data( devcfg__INT_MASK, val_devcfg__INT_MASK);
set_reset_data( devcfg__STATUS, val_devcfg__STATUS);
set_reset_data( devcfg__DMA_SRC_ADDR, val_devcfg__DMA_SRC_ADDR);
set_reset_data( devcfg__DMA_DST_ADDR, val_devcfg__DMA_DST_ADDR);
set_reset_data( devcfg__DMA_SRC_LEN, val_devcfg__DMA_SRC_LEN);
set_reset_data( devcfg__DMA_DEST_LEN, val_devcfg__DMA_DEST_LEN);
set_reset_data( devcfg__ROM_SHADOW, val_devcfg__ROM_SHADOW);
set_reset_data( devcfg__MULTIBOOT_ADDR, val_devcfg__MULTIBOOT_ADDR);
set_reset_data( devcfg__SW_ID, val_devcfg__SW_ID);
set_reset_data( devcfg__UNLOCK, val_devcfg__UNLOCK);
set_reset_data( devcfg__MCTRL, val_devcfg__MCTRL);
set_reset_data( devcfg__XADCIF_CFG, val_devcfg__XADCIF_CFG);
set_reset_data( devcfg__XADCIF_INT_STS, val_devcfg__XADCIF_INT_STS);
set_reset_data( devcfg__XADCIF_INT_MASK, val_devcfg__XADCIF_INT_MASK);
set_reset_data( devcfg__XADCIF_MSTS, val_devcfg__XADCIF_MSTS);
set_reset_data( devcfg__XADCIF_CMDFIFO, val_devcfg__XADCIF_CMDFIFO);
set_reset_data( devcfg__XADCIF_RDFIFO, val_devcfg__XADCIF_RDFIFO);
set_reset_data( devcfg__XADCIF_MCTL, val_devcfg__XADCIF_MCTL);

// ************************************************************
//   Module dmac0_ns dmac
//   doc version: 1.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( dmac0_ns__DSR, val_dmac0_ns__DSR);
set_reset_data( dmac0_ns__DPC, val_dmac0_ns__DPC);
set_reset_data( dmac0_ns__INTEN, val_dmac0_ns__INTEN);
set_reset_data( dmac0_ns__INT_EVENT_RIS, val_dmac0_ns__INT_EVENT_RIS);
set_reset_data( dmac0_ns__INTMIS, val_dmac0_ns__INTMIS);
set_reset_data( dmac0_ns__INTCLR, val_dmac0_ns__INTCLR);
set_reset_data( dmac0_ns__FSRD, val_dmac0_ns__FSRD);
set_reset_data( dmac0_ns__FSRC, val_dmac0_ns__FSRC);
set_reset_data( dmac0_ns__FTRD, val_dmac0_ns__FTRD);
set_reset_data( dmac0_ns__FTR0, val_dmac0_ns__FTR0);
set_reset_data( dmac0_ns__FTR1, val_dmac0_ns__FTR1);
set_reset_data( dmac0_ns__FTR2, val_dmac0_ns__FTR2);
set_reset_data( dmac0_ns__FTR3, val_dmac0_ns__FTR3);
set_reset_data( dmac0_ns__FTR4, val_dmac0_ns__FTR4);
set_reset_data( dmac0_ns__FTR5, val_dmac0_ns__FTR5);
set_reset_data( dmac0_ns__FTR6, val_dmac0_ns__FTR6);
set_reset_data( dmac0_ns__FTR7, val_dmac0_ns__FTR7);
set_reset_data( dmac0_ns__CSR0, val_dmac0_ns__CSR0);
set_reset_data( dmac0_ns__CPC0, val_dmac0_ns__CPC0);
set_reset_data( dmac0_ns__CSR1, val_dmac0_ns__CSR1);
set_reset_data( dmac0_ns__CPC1, val_dmac0_ns__CPC1);
set_reset_data( dmac0_ns__CSR2, val_dmac0_ns__CSR2);
set_reset_data( dmac0_ns__CPC2, val_dmac0_ns__CPC2);
set_reset_data( dmac0_ns__CSR3, val_dmac0_ns__CSR3);
set_reset_data( dmac0_ns__CPC3, val_dmac0_ns__CPC3);
set_reset_data( dmac0_ns__CSR4, val_dmac0_ns__CSR4);
set_reset_data( dmac0_ns__CPC4, val_dmac0_ns__CPC4);
set_reset_data( dmac0_ns__CSR5, val_dmac0_ns__CSR5);
set_reset_data( dmac0_ns__CPC5, val_dmac0_ns__CPC5);
set_reset_data( dmac0_ns__CSR6, val_dmac0_ns__CSR6);
set_reset_data( dmac0_ns__CPC6, val_dmac0_ns__CPC6);
set_reset_data( dmac0_ns__CSR7, val_dmac0_ns__CSR7);
set_reset_data( dmac0_ns__CPC7, val_dmac0_ns__CPC7);
set_reset_data( dmac0_ns__SAR0, val_dmac0_ns__SAR0);
set_reset_data( dmac0_ns__DAR0, val_dmac0_ns__DAR0);
set_reset_data( dmac0_ns__CCR0, val_dmac0_ns__CCR0);
set_reset_data( dmac0_ns__LC0_0, val_dmac0_ns__LC0_0);
set_reset_data( dmac0_ns__LC1_0, val_dmac0_ns__LC1_0);
set_reset_data( dmac0_ns__SAR1, val_dmac0_ns__SAR1);
set_reset_data( dmac0_ns__DAR1, val_dmac0_ns__DAR1);
set_reset_data( dmac0_ns__CCR1, val_dmac0_ns__CCR1);
set_reset_data( dmac0_ns__LC0_1, val_dmac0_ns__LC0_1);
set_reset_data( dmac0_ns__LC1_1, val_dmac0_ns__LC1_1);
set_reset_data( dmac0_ns__SAR2, val_dmac0_ns__SAR2);
set_reset_data( dmac0_ns__DAR2, val_dmac0_ns__DAR2);
set_reset_data( dmac0_ns__CCR2, val_dmac0_ns__CCR2);
set_reset_data( dmac0_ns__LC0_2, val_dmac0_ns__LC0_2);
set_reset_data( dmac0_ns__LC1_2, val_dmac0_ns__LC1_2);
set_reset_data( dmac0_ns__SAR3, val_dmac0_ns__SAR3);
set_reset_data( dmac0_ns__DAR3, val_dmac0_ns__DAR3);
set_reset_data( dmac0_ns__CCR3, val_dmac0_ns__CCR3);
set_reset_data( dmac0_ns__LC0_3, val_dmac0_ns__LC0_3);
set_reset_data( dmac0_ns__LC1_3, val_dmac0_ns__LC1_3);
set_reset_data( dmac0_ns__SAR4, val_dmac0_ns__SAR4);
set_reset_data( dmac0_ns__DAR4, val_dmac0_ns__DAR4);
set_reset_data( dmac0_ns__CCR4, val_dmac0_ns__CCR4);
set_reset_data( dmac0_ns__LC0_4, val_dmac0_ns__LC0_4);
set_reset_data( dmac0_ns__LC1_4, val_dmac0_ns__LC1_4);
set_reset_data( dmac0_ns__SAR5, val_dmac0_ns__SAR5);
set_reset_data( dmac0_ns__DAR5, val_dmac0_ns__DAR5);
set_reset_data( dmac0_ns__CCR5, val_dmac0_ns__CCR5);
set_reset_data( dmac0_ns__LC0_5, val_dmac0_ns__LC0_5);
set_reset_data( dmac0_ns__LC1_5, val_dmac0_ns__LC1_5);
set_reset_data( dmac0_ns__SAR6, val_dmac0_ns__SAR6);
set_reset_data( dmac0_ns__DAR6, val_dmac0_ns__DAR6);
set_reset_data( dmac0_ns__CCR6, val_dmac0_ns__CCR6);
set_reset_data( dmac0_ns__LC0_6, val_dmac0_ns__LC0_6);
set_reset_data( dmac0_ns__LC1_6, val_dmac0_ns__LC1_6);
set_reset_data( dmac0_ns__SAR7, val_dmac0_ns__SAR7);
set_reset_data( dmac0_ns__DAR7, val_dmac0_ns__DAR7);
set_reset_data( dmac0_ns__CCR7, val_dmac0_ns__CCR7);
set_reset_data( dmac0_ns__LC0_7, val_dmac0_ns__LC0_7);
set_reset_data( dmac0_ns__LC1_7, val_dmac0_ns__LC1_7);
set_reset_data( dmac0_ns__DBGSTATUS, val_dmac0_ns__DBGSTATUS);
set_reset_data( dmac0_ns__DBGCMD, val_dmac0_ns__DBGCMD);
set_reset_data( dmac0_ns__DBGINST0, val_dmac0_ns__DBGINST0);
set_reset_data( dmac0_ns__DBGINST1, val_dmac0_ns__DBGINST1);
set_reset_data( dmac0_ns__CR0, val_dmac0_ns__CR0);
set_reset_data( dmac0_ns__CR1, val_dmac0_ns__CR1);
set_reset_data( dmac0_ns__CR2, val_dmac0_ns__CR2);
set_reset_data( dmac0_ns__CR3, val_dmac0_ns__CR3);
set_reset_data( dmac0_ns__CR4, val_dmac0_ns__CR4);
set_reset_data( dmac0_ns__CRD, val_dmac0_ns__CRD);
set_reset_data( dmac0_ns__WD, val_dmac0_ns__WD);
set_reset_data( dmac0_ns__periph_id_0, val_dmac0_ns__periph_id_0);
set_reset_data( dmac0_ns__periph_id_1, val_dmac0_ns__periph_id_1);
set_reset_data( dmac0_ns__periph_id_2, val_dmac0_ns__periph_id_2);
set_reset_data( dmac0_ns__periph_id_3, val_dmac0_ns__periph_id_3);
set_reset_data( dmac0_ns__pcell_id_0, val_dmac0_ns__pcell_id_0);
set_reset_data( dmac0_ns__pcell_id_1, val_dmac0_ns__pcell_id_1);
set_reset_data( dmac0_ns__pcell_id_2, val_dmac0_ns__pcell_id_2);
set_reset_data( dmac0_ns__pcell_id_3, val_dmac0_ns__pcell_id_3);

// ************************************************************
//   Module dmac0_s dmac
//   doc version: 1.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( dmac0_s__DSR, val_dmac0_s__DSR);
set_reset_data( dmac0_s__DPC, val_dmac0_s__DPC);
set_reset_data( dmac0_s__INTEN, val_dmac0_s__INTEN);
set_reset_data( dmac0_s__INT_EVENT_RIS, val_dmac0_s__INT_EVENT_RIS);
set_reset_data( dmac0_s__INTMIS, val_dmac0_s__INTMIS);
set_reset_data( dmac0_s__INTCLR, val_dmac0_s__INTCLR);
set_reset_data( dmac0_s__FSRD, val_dmac0_s__FSRD);
set_reset_data( dmac0_s__FSRC, val_dmac0_s__FSRC);
set_reset_data( dmac0_s__FTRD, val_dmac0_s__FTRD);
set_reset_data( dmac0_s__FTR0, val_dmac0_s__FTR0);
set_reset_data( dmac0_s__FTR1, val_dmac0_s__FTR1);
set_reset_data( dmac0_s__FTR2, val_dmac0_s__FTR2);
set_reset_data( dmac0_s__FTR3, val_dmac0_s__FTR3);
set_reset_data( dmac0_s__FTR4, val_dmac0_s__FTR4);
set_reset_data( dmac0_s__FTR5, val_dmac0_s__FTR5);
set_reset_data( dmac0_s__FTR6, val_dmac0_s__FTR6);
set_reset_data( dmac0_s__FTR7, val_dmac0_s__FTR7);
set_reset_data( dmac0_s__CSR0, val_dmac0_s__CSR0);
set_reset_data( dmac0_s__CPC0, val_dmac0_s__CPC0);
set_reset_data( dmac0_s__CSR1, val_dmac0_s__CSR1);
set_reset_data( dmac0_s__CPC1, val_dmac0_s__CPC1);
set_reset_data( dmac0_s__CSR2, val_dmac0_s__CSR2);
set_reset_data( dmac0_s__CPC2, val_dmac0_s__CPC2);
set_reset_data( dmac0_s__CSR3, val_dmac0_s__CSR3);
set_reset_data( dmac0_s__CPC3, val_dmac0_s__CPC3);
set_reset_data( dmac0_s__CSR4, val_dmac0_s__CSR4);
set_reset_data( dmac0_s__CPC4, val_dmac0_s__CPC4);
set_reset_data( dmac0_s__CSR5, val_dmac0_s__CSR5);
set_reset_data( dmac0_s__CPC5, val_dmac0_s__CPC5);
set_reset_data( dmac0_s__CSR6, val_dmac0_s__CSR6);
set_reset_data( dmac0_s__CPC6, val_dmac0_s__CPC6);
set_reset_data( dmac0_s__CSR7, val_dmac0_s__CSR7);
set_reset_data( dmac0_s__CPC7, val_dmac0_s__CPC7);
set_reset_data( dmac0_s__SAR0, val_dmac0_s__SAR0);
set_reset_data( dmac0_s__DAR0, val_dmac0_s__DAR0);
set_reset_data( dmac0_s__CCR0, val_dmac0_s__CCR0);
set_reset_data( dmac0_s__LC0_0, val_dmac0_s__LC0_0);
set_reset_data( dmac0_s__LC1_0, val_dmac0_s__LC1_0);
set_reset_data( dmac0_s__SAR1, val_dmac0_s__SAR1);
set_reset_data( dmac0_s__DAR1, val_dmac0_s__DAR1);
set_reset_data( dmac0_s__CCR1, val_dmac0_s__CCR1);
set_reset_data( dmac0_s__LC0_1, val_dmac0_s__LC0_1);
set_reset_data( dmac0_s__LC1_1, val_dmac0_s__LC1_1);
set_reset_data( dmac0_s__SAR2, val_dmac0_s__SAR2);
set_reset_data( dmac0_s__DAR2, val_dmac0_s__DAR2);
set_reset_data( dmac0_s__CCR2, val_dmac0_s__CCR2);
set_reset_data( dmac0_s__LC0_2, val_dmac0_s__LC0_2);
set_reset_data( dmac0_s__LC1_2, val_dmac0_s__LC1_2);
set_reset_data( dmac0_s__SAR3, val_dmac0_s__SAR3);
set_reset_data( dmac0_s__DAR3, val_dmac0_s__DAR3);
set_reset_data( dmac0_s__CCR3, val_dmac0_s__CCR3);
set_reset_data( dmac0_s__LC0_3, val_dmac0_s__LC0_3);
set_reset_data( dmac0_s__LC1_3, val_dmac0_s__LC1_3);
set_reset_data( dmac0_s__SAR4, val_dmac0_s__SAR4);
set_reset_data( dmac0_s__DAR4, val_dmac0_s__DAR4);
set_reset_data( dmac0_s__CCR4, val_dmac0_s__CCR4);
set_reset_data( dmac0_s__LC0_4, val_dmac0_s__LC0_4);
set_reset_data( dmac0_s__LC1_4, val_dmac0_s__LC1_4);
set_reset_data( dmac0_s__SAR5, val_dmac0_s__SAR5);
set_reset_data( dmac0_s__DAR5, val_dmac0_s__DAR5);
set_reset_data( dmac0_s__CCR5, val_dmac0_s__CCR5);
set_reset_data( dmac0_s__LC0_5, val_dmac0_s__LC0_5);
set_reset_data( dmac0_s__LC1_5, val_dmac0_s__LC1_5);
set_reset_data( dmac0_s__SAR6, val_dmac0_s__SAR6);
set_reset_data( dmac0_s__DAR6, val_dmac0_s__DAR6);
set_reset_data( dmac0_s__CCR6, val_dmac0_s__CCR6);
set_reset_data( dmac0_s__LC0_6, val_dmac0_s__LC0_6);
set_reset_data( dmac0_s__LC1_6, val_dmac0_s__LC1_6);
set_reset_data( dmac0_s__SAR7, val_dmac0_s__SAR7);
set_reset_data( dmac0_s__DAR7, val_dmac0_s__DAR7);
set_reset_data( dmac0_s__CCR7, val_dmac0_s__CCR7);
set_reset_data( dmac0_s__LC0_7, val_dmac0_s__LC0_7);
set_reset_data( dmac0_s__LC1_7, val_dmac0_s__LC1_7);
set_reset_data( dmac0_s__DBGSTATUS, val_dmac0_s__DBGSTATUS);
set_reset_data( dmac0_s__DBGCMD, val_dmac0_s__DBGCMD);
set_reset_data( dmac0_s__DBGINST0, val_dmac0_s__DBGINST0);
set_reset_data( dmac0_s__DBGINST1, val_dmac0_s__DBGINST1);
set_reset_data( dmac0_s__CR0, val_dmac0_s__CR0);
set_reset_data( dmac0_s__CR1, val_dmac0_s__CR1);
set_reset_data( dmac0_s__CR2, val_dmac0_s__CR2);
set_reset_data( dmac0_s__CR3, val_dmac0_s__CR3);
set_reset_data( dmac0_s__CR4, val_dmac0_s__CR4);
set_reset_data( dmac0_s__CRD, val_dmac0_s__CRD);
set_reset_data( dmac0_s__WD, val_dmac0_s__WD);
set_reset_data( dmac0_s__periph_id_0, val_dmac0_s__periph_id_0);
set_reset_data( dmac0_s__periph_id_1, val_dmac0_s__periph_id_1);
set_reset_data( dmac0_s__periph_id_2, val_dmac0_s__periph_id_2);
set_reset_data( dmac0_s__periph_id_3, val_dmac0_s__periph_id_3);
set_reset_data( dmac0_s__pcell_id_0, val_dmac0_s__pcell_id_0);
set_reset_data( dmac0_s__pcell_id_1, val_dmac0_s__pcell_id_1);
set_reset_data( dmac0_s__pcell_id_2, val_dmac0_s__pcell_id_2);
set_reset_data( dmac0_s__pcell_id_3, val_dmac0_s__pcell_id_3);

// ************************************************************
//   Module efuse_ctrl efuse_ctrl
//   doc version: 1.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( efuse_ctrl__WR_LOCK, val_efuse_ctrl__WR_LOCK);
set_reset_data( efuse_ctrl__WR_UNLOCK, val_efuse_ctrl__WR_UNLOCK);
set_reset_data( efuse_ctrl__WR_LOCKSTA, val_efuse_ctrl__WR_LOCKSTA);
set_reset_data( efuse_ctrl__CFG, val_efuse_ctrl__CFG);
set_reset_data( efuse_ctrl__STATUS, val_efuse_ctrl__STATUS);
set_reset_data( efuse_ctrl__CONTROL, val_efuse_ctrl__CONTROL);
set_reset_data( efuse_ctrl__PGM_STBW, val_efuse_ctrl__PGM_STBW);
set_reset_data( efuse_ctrl__RD_STBW, val_efuse_ctrl__RD_STBW);

// ************************************************************
//   Module gem0 GEM
//   doc version: 
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( gem0__net_ctrl, val_gem0__net_ctrl);
set_reset_data( gem0__net_cfg, val_gem0__net_cfg);
set_reset_data( gem0__net_status, val_gem0__net_status);
set_reset_data( gem0__user_io, val_gem0__user_io);
set_reset_data( gem0__dma_cfg, val_gem0__dma_cfg);
set_reset_data( gem0__tx_status, val_gem0__tx_status);
set_reset_data( gem0__rx_qbar, val_gem0__rx_qbar);
set_reset_data( gem0__tx_qbar, val_gem0__tx_qbar);
set_reset_data( gem0__rx_status, val_gem0__rx_status);
set_reset_data( gem0__intr_status, val_gem0__intr_status);
set_reset_data( gem0__intr_en, val_gem0__intr_en);
set_reset_data( gem0__intr_dis, val_gem0__intr_dis);
set_reset_data( gem0__intr_mask, val_gem0__intr_mask);
set_reset_data( gem0__phy_maint, val_gem0__phy_maint);
set_reset_data( gem0__rx_pauseq, val_gem0__rx_pauseq);
set_reset_data( gem0__tx_pauseq, val_gem0__tx_pauseq);
set_reset_data( gem0__tx_partial_st_fwd, val_gem0__tx_partial_st_fwd);
set_reset_data( gem0__rx_partial_st_fwd, val_gem0__rx_partial_st_fwd);
set_reset_data( gem0__hash_bot, val_gem0__hash_bot);
set_reset_data( gem0__hash_top, val_gem0__hash_top);
set_reset_data( gem0__spec_addr1_bot, val_gem0__spec_addr1_bot);
set_reset_data( gem0__spec_addr1_top, val_gem0__spec_addr1_top);
set_reset_data( gem0__spec_addr2_bot, val_gem0__spec_addr2_bot);
set_reset_data( gem0__spec_addr2_top, val_gem0__spec_addr2_top);
set_reset_data( gem0__spec_addr3_bot, val_gem0__spec_addr3_bot);
set_reset_data( gem0__spec_addr3_top, val_gem0__spec_addr3_top);
set_reset_data( gem0__spec_addr4_bot, val_gem0__spec_addr4_bot);
set_reset_data( gem0__spec_addr4_top, val_gem0__spec_addr4_top);
set_reset_data( gem0__type_id_match1, val_gem0__type_id_match1);
set_reset_data( gem0__type_id_match2, val_gem0__type_id_match2);
set_reset_data( gem0__type_id_match3, val_gem0__type_id_match3);
set_reset_data( gem0__type_id_match4, val_gem0__type_id_match4);
set_reset_data( gem0__wake_on_lan, val_gem0__wake_on_lan);
set_reset_data( gem0__ipg_stretch, val_gem0__ipg_stretch);
set_reset_data( gem0__stacked_vlan, val_gem0__stacked_vlan);
set_reset_data( gem0__tx_pfc_pause, val_gem0__tx_pfc_pause);
set_reset_data( gem0__spec_addr1_mask_bot, val_gem0__spec_addr1_mask_bot);
set_reset_data( gem0__spec_addr1_mask_top, val_gem0__spec_addr1_mask_top);
set_reset_data( gem0__module_id, val_gem0__module_id);
set_reset_data( gem0__octets_tx_bot, val_gem0__octets_tx_bot);
set_reset_data( gem0__octets_tx_top, val_gem0__octets_tx_top);
set_reset_data( gem0__frames_tx, val_gem0__frames_tx);
set_reset_data( gem0__broadcast_frames_tx, val_gem0__broadcast_frames_tx);
set_reset_data( gem0__multi_frames_tx, val_gem0__multi_frames_tx);
set_reset_data( gem0__pause_frames_tx, val_gem0__pause_frames_tx);
set_reset_data( gem0__frames_64b_tx, val_gem0__frames_64b_tx);
set_reset_data( gem0__frames_65to127b_tx, val_gem0__frames_65to127b_tx);
set_reset_data( gem0__frames_128to255b_tx, val_gem0__frames_128to255b_tx);
set_reset_data( gem0__frames_256to511b_tx, val_gem0__frames_256to511b_tx);
set_reset_data( gem0__frames_512to1023b_tx, val_gem0__frames_512to1023b_tx);
set_reset_data( gem0__frames_1024to1518b_tx, val_gem0__frames_1024to1518b_tx);
set_reset_data( gem0__frames_gt1518b_tx, val_gem0__frames_gt1518b_tx);
set_reset_data( gem0__tx_under_runs, val_gem0__tx_under_runs);
set_reset_data( gem0__single_collisn_frames, val_gem0__single_collisn_frames);
set_reset_data( gem0__multi_collisn_frames, val_gem0__multi_collisn_frames);
set_reset_data( gem0__excessive_collisns, val_gem0__excessive_collisns);
set_reset_data( gem0__late_collisns, val_gem0__late_collisns);
set_reset_data( gem0__deferred_tx_frames, val_gem0__deferred_tx_frames);
set_reset_data( gem0__carrier_sense_errs, val_gem0__carrier_sense_errs);
set_reset_data( gem0__octets_rx_bot, val_gem0__octets_rx_bot);
set_reset_data( gem0__octets_rx_top, val_gem0__octets_rx_top);
set_reset_data( gem0__frames_rx, val_gem0__frames_rx);
set_reset_data( gem0__bdcast_fames_rx, val_gem0__bdcast_fames_rx);
set_reset_data( gem0__multi_frames_rx, val_gem0__multi_frames_rx);
set_reset_data( gem0__pause_rx, val_gem0__pause_rx);
set_reset_data( gem0__frames_64b_rx, val_gem0__frames_64b_rx);
set_reset_data( gem0__frames_65to127b_rx, val_gem0__frames_65to127b_rx);
set_reset_data( gem0__frames_128to255b_rx, val_gem0__frames_128to255b_rx);
set_reset_data( gem0__frames_256to511b_rx, val_gem0__frames_256to511b_rx);
set_reset_data( gem0__frames_512to1023b_rx, val_gem0__frames_512to1023b_rx);
set_reset_data( gem0__frames_1024to1518b_rx, val_gem0__frames_1024to1518b_rx);
set_reset_data( gem0__frames_gt1518b_rx, val_gem0__frames_gt1518b_rx);
set_reset_data( gem0__undersz_rx, val_gem0__undersz_rx);
set_reset_data( gem0__oversz_rx, val_gem0__oversz_rx);
set_reset_data( gem0__jab_rx, val_gem0__jab_rx);
set_reset_data( gem0__fcs_errors, val_gem0__fcs_errors);
set_reset_data( gem0__length_field_errors, val_gem0__length_field_errors);
set_reset_data( gem0__rx_symbol_errors, val_gem0__rx_symbol_errors);
set_reset_data( gem0__align_errors, val_gem0__align_errors);
set_reset_data( gem0__rx_resource_errors, val_gem0__rx_resource_errors);
set_reset_data( gem0__rx_overrun_errors, val_gem0__rx_overrun_errors);
set_reset_data( gem0__ip_hdr_csum_errors, val_gem0__ip_hdr_csum_errors);
set_reset_data( gem0__tcp_csum_errors, val_gem0__tcp_csum_errors);
set_reset_data( gem0__udp_csum_errors, val_gem0__udp_csum_errors);
set_reset_data( gem0__timer_strobe_s, val_gem0__timer_strobe_s);
set_reset_data( gem0__timer_strobe_ns, val_gem0__timer_strobe_ns);
set_reset_data( gem0__timer_s, val_gem0__timer_s);
set_reset_data( gem0__timer_ns, val_gem0__timer_ns);
set_reset_data( gem0__timer_adjust, val_gem0__timer_adjust);
set_reset_data( gem0__timer_incr, val_gem0__timer_incr);
set_reset_data( gem0__ptp_tx_s, val_gem0__ptp_tx_s);
set_reset_data( gem0__ptp_tx_ns, val_gem0__ptp_tx_ns);
set_reset_data( gem0__ptp_rx_s, val_gem0__ptp_rx_s);
set_reset_data( gem0__ptp_rx_ns, val_gem0__ptp_rx_ns);
set_reset_data( gem0__ptp_peer_tx_s, val_gem0__ptp_peer_tx_s);
set_reset_data( gem0__ptp_peer_tx_ns, val_gem0__ptp_peer_tx_ns);
set_reset_data( gem0__ptp_peer_rx_s, val_gem0__ptp_peer_rx_s);
set_reset_data( gem0__ptp_peer_rx_ns, val_gem0__ptp_peer_rx_ns);
set_reset_data( gem0__pcs_ctrl, val_gem0__pcs_ctrl);
set_reset_data( gem0__pcs_status, val_gem0__pcs_status);
set_reset_data( gem0__pcs_upper_phy_id, val_gem0__pcs_upper_phy_id);
set_reset_data( gem0__pcs_lower_phy_id, val_gem0__pcs_lower_phy_id);
set_reset_data( gem0__pcs_autoneg_ad, val_gem0__pcs_autoneg_ad);
set_reset_data( gem0__pcs_autoneg_ability, val_gem0__pcs_autoneg_ability);
set_reset_data( gem0__pcs_autonec_exp, val_gem0__pcs_autonec_exp);
set_reset_data( gem0__pcs_autoneg_next_pg, val_gem0__pcs_autoneg_next_pg);
set_reset_data( gem0__pcs_autoneg_pnext_pg, val_gem0__pcs_autoneg_pnext_pg);
set_reset_data( gem0__pcs_extended_status, val_gem0__pcs_extended_status);
set_reset_data( gem0__design_cfg1, val_gem0__design_cfg1);
set_reset_data( gem0__design_cfg2, val_gem0__design_cfg2);
set_reset_data( gem0__design_cfg3, val_gem0__design_cfg3);
set_reset_data( gem0__design_cfg4, val_gem0__design_cfg4);
set_reset_data( gem0__design_cfg5, val_gem0__design_cfg5);
set_reset_data( gem0__design_cfg6, val_gem0__design_cfg6);
set_reset_data( gem0__design_cfg7, val_gem0__design_cfg7);
set_reset_data( gem0__isr_pq1, val_gem0__isr_pq1);
set_reset_data( gem0__isr_pq2, val_gem0__isr_pq2);
set_reset_data( gem0__isr_pq3, val_gem0__isr_pq3);
set_reset_data( gem0__isr_pq4, val_gem0__isr_pq4);
set_reset_data( gem0__isr_pq5, val_gem0__isr_pq5);
set_reset_data( gem0__isr_pq6, val_gem0__isr_pq6);
set_reset_data( gem0__isr_pq7, val_gem0__isr_pq7);
set_reset_data( gem0__tx_qbar_q1, val_gem0__tx_qbar_q1);
set_reset_data( gem0__tx_qbar_q2, val_gem0__tx_qbar_q2);
set_reset_data( gem0__tx_qbar_q3, val_gem0__tx_qbar_q3);
set_reset_data( gem0__tx_qbar_q4, val_gem0__tx_qbar_q4);
set_reset_data( gem0__tx_qbar_q5, val_gem0__tx_qbar_q5);
set_reset_data( gem0__tx_qbar_q6, val_gem0__tx_qbar_q6);
set_reset_data( gem0__tx_qbar_q7, val_gem0__tx_qbar_q7);
set_reset_data( gem0__rx_qbar_q1, val_gem0__rx_qbar_q1);
set_reset_data( gem0__rx_qbar_q2, val_gem0__rx_qbar_q2);
set_reset_data( gem0__rx_qbar_q3, val_gem0__rx_qbar_q3);
set_reset_data( gem0__rx_qbar_q4, val_gem0__rx_qbar_q4);
set_reset_data( gem0__rx_qbar_q5, val_gem0__rx_qbar_q5);
set_reset_data( gem0__rx_qbar_q6, val_gem0__rx_qbar_q6);
set_reset_data( gem0__rx_qbar_q7, val_gem0__rx_qbar_q7);
set_reset_data( gem0__rx_bufsz_q1, val_gem0__rx_bufsz_q1);
set_reset_data( gem0__rx_bufsz_q2, val_gem0__rx_bufsz_q2);
set_reset_data( gem0__rx_bufsz_q3, val_gem0__rx_bufsz_q3);
set_reset_data( gem0__rx_bufsz_q4, val_gem0__rx_bufsz_q4);
set_reset_data( gem0__rx_bufsz_q5, val_gem0__rx_bufsz_q5);
set_reset_data( gem0__rx_bufsz_q6, val_gem0__rx_bufsz_q6);
set_reset_data( gem0__rx_bufsz_q7, val_gem0__rx_bufsz_q7);
set_reset_data( gem0__screen_t1_r0, val_gem0__screen_t1_r0);
set_reset_data( gem0__screen_t1_r1, val_gem0__screen_t1_r1);
set_reset_data( gem0__screen_t1_r2, val_gem0__screen_t1_r2);
set_reset_data( gem0__screen_t1_r3, val_gem0__screen_t1_r3);
set_reset_data( gem0__screen_t1_r4, val_gem0__screen_t1_r4);
set_reset_data( gem0__screen_t1_r5, val_gem0__screen_t1_r5);
set_reset_data( gem0__screen_t1_r6, val_gem0__screen_t1_r6);
set_reset_data( gem0__screen_t1_r7, val_gem0__screen_t1_r7);
set_reset_data( gem0__screen_t1_r8, val_gem0__screen_t1_r8);
set_reset_data( gem0__screen_t1_r9, val_gem0__screen_t1_r9);
set_reset_data( gem0__screen_t1_r10, val_gem0__screen_t1_r10);
set_reset_data( gem0__screen_t1_r11, val_gem0__screen_t1_r11);
set_reset_data( gem0__screen_t1_r12, val_gem0__screen_t1_r12);
set_reset_data( gem0__screen_t1_r13, val_gem0__screen_t1_r13);
set_reset_data( gem0__screen_t1_r14, val_gem0__screen_t1_r14);
set_reset_data( gem0__screen_t1_r15, val_gem0__screen_t1_r15);
set_reset_data( gem0__screen_t2_r0, val_gem0__screen_t2_r0);
set_reset_data( gem0__screen_t2_r1, val_gem0__screen_t2_r1);
set_reset_data( gem0__screen_t2_r2, val_gem0__screen_t2_r2);
set_reset_data( gem0__screen_t2_r3, val_gem0__screen_t2_r3);
set_reset_data( gem0__screen_t2_r4, val_gem0__screen_t2_r4);
set_reset_data( gem0__screen_t2_r5, val_gem0__screen_t2_r5);
set_reset_data( gem0__screen_t2_r6, val_gem0__screen_t2_r6);
set_reset_data( gem0__screen_t2_r7, val_gem0__screen_t2_r7);
set_reset_data( gem0__screen_t2_r8, val_gem0__screen_t2_r8);
set_reset_data( gem0__screen_t2_r9, val_gem0__screen_t2_r9);
set_reset_data( gem0__screen_t2_r10, val_gem0__screen_t2_r10);
set_reset_data( gem0__screen_t2_r11, val_gem0__screen_t2_r11);
set_reset_data( gem0__screen_t2_r12, val_gem0__screen_t2_r12);
set_reset_data( gem0__screen_t2_r13, val_gem0__screen_t2_r13);
set_reset_data( gem0__screen_t2_r14, val_gem0__screen_t2_r14);
set_reset_data( gem0__screen_t2_r15, val_gem0__screen_t2_r15);
set_reset_data( gem0__intr_en_pq1, val_gem0__intr_en_pq1);
set_reset_data( gem0__intr_en_pq2, val_gem0__intr_en_pq2);
set_reset_data( gem0__intr_en_pq3, val_gem0__intr_en_pq3);
set_reset_data( gem0__intr_en_pq4, val_gem0__intr_en_pq4);
set_reset_data( gem0__intr_en_pq5, val_gem0__intr_en_pq5);
set_reset_data( gem0__intr_en_pq6, val_gem0__intr_en_pq6);
set_reset_data( gem0__intr_en_pq7, val_gem0__intr_en_pq7);
set_reset_data( gem0__intr_dis_pq1, val_gem0__intr_dis_pq1);
set_reset_data( gem0__intr_dis_pq2, val_gem0__intr_dis_pq2);
set_reset_data( gem0__intr_dis_pq3, val_gem0__intr_dis_pq3);
set_reset_data( gem0__intr_dis_pq4, val_gem0__intr_dis_pq4);
set_reset_data( gem0__intr_dis_pq5, val_gem0__intr_dis_pq5);
set_reset_data( gem0__intr_dis_pq6, val_gem0__intr_dis_pq6);
set_reset_data( gem0__intr_dis_pq7, val_gem0__intr_dis_pq7);
set_reset_data( gem0__intr_mask_pq1, val_gem0__intr_mask_pq1);
set_reset_data( gem0__intr_mask_pq2, val_gem0__intr_mask_pq2);
set_reset_data( gem0__intr_mask_pq3, val_gem0__intr_mask_pq3);
set_reset_data( gem0__intr_mask_pq4, val_gem0__intr_mask_pq4);
set_reset_data( gem0__intr_mask_pq5, val_gem0__intr_mask_pq5);
set_reset_data( gem0__intr_mask_pq6, val_gem0__intr_mask_pq6);
set_reset_data( gem0__intr_mask_pq7, val_gem0__intr_mask_pq7);

// ************************************************************
//   Module gem1 GEM
//   doc version: 
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( gem1__net_ctrl, val_gem1__net_ctrl);
set_reset_data( gem1__net_cfg, val_gem1__net_cfg);
set_reset_data( gem1__net_status, val_gem1__net_status);
set_reset_data( gem1__user_io, val_gem1__user_io);
set_reset_data( gem1__dma_cfg, val_gem1__dma_cfg);
set_reset_data( gem1__tx_status, val_gem1__tx_status);
set_reset_data( gem1__rx_qbar, val_gem1__rx_qbar);
set_reset_data( gem1__tx_qbar, val_gem1__tx_qbar);
set_reset_data( gem1__rx_status, val_gem1__rx_status);
set_reset_data( gem1__intr_status, val_gem1__intr_status);
set_reset_data( gem1__intr_en, val_gem1__intr_en);
set_reset_data( gem1__intr_dis, val_gem1__intr_dis);
set_reset_data( gem1__intr_mask, val_gem1__intr_mask);
set_reset_data( gem1__phy_maint, val_gem1__phy_maint);
set_reset_data( gem1__rx_pauseq, val_gem1__rx_pauseq);
set_reset_data( gem1__tx_pauseq, val_gem1__tx_pauseq);
set_reset_data( gem1__tx_partial_st_fwd, val_gem1__tx_partial_st_fwd);
set_reset_data( gem1__rx_partial_st_fwd, val_gem1__rx_partial_st_fwd);
set_reset_data( gem1__hash_bot, val_gem1__hash_bot);
set_reset_data( gem1__hash_top, val_gem1__hash_top);
set_reset_data( gem1__spec_addr1_bot, val_gem1__spec_addr1_bot);
set_reset_data( gem1__spec_addr1_top, val_gem1__spec_addr1_top);
set_reset_data( gem1__spec_addr2_bot, val_gem1__spec_addr2_bot);
set_reset_data( gem1__spec_addr2_top, val_gem1__spec_addr2_top);
set_reset_data( gem1__spec_addr3_bot, val_gem1__spec_addr3_bot);
set_reset_data( gem1__spec_addr3_top, val_gem1__spec_addr3_top);
set_reset_data( gem1__spec_addr4_bot, val_gem1__spec_addr4_bot);
set_reset_data( gem1__spec_addr4_top, val_gem1__spec_addr4_top);
set_reset_data( gem1__type_id_match1, val_gem1__type_id_match1);
set_reset_data( gem1__type_id_match2, val_gem1__type_id_match2);
set_reset_data( gem1__type_id_match3, val_gem1__type_id_match3);
set_reset_data( gem1__type_id_match4, val_gem1__type_id_match4);
set_reset_data( gem1__wake_on_lan, val_gem1__wake_on_lan);
set_reset_data( gem1__ipg_stretch, val_gem1__ipg_stretch);
set_reset_data( gem1__stacked_vlan, val_gem1__stacked_vlan);
set_reset_data( gem1__tx_pfc_pause, val_gem1__tx_pfc_pause);
set_reset_data( gem1__spec_addr1_mask_bot, val_gem1__spec_addr1_mask_bot);
set_reset_data( gem1__spec_addr1_mask_top, val_gem1__spec_addr1_mask_top);
set_reset_data( gem1__module_id, val_gem1__module_id);
set_reset_data( gem1__octets_tx_bot, val_gem1__octets_tx_bot);
set_reset_data( gem1__octets_tx_top, val_gem1__octets_tx_top);
set_reset_data( gem1__frames_tx, val_gem1__frames_tx);
set_reset_data( gem1__broadcast_frames_tx, val_gem1__broadcast_frames_tx);
set_reset_data( gem1__multi_frames_tx, val_gem1__multi_frames_tx);
set_reset_data( gem1__pause_frames_tx, val_gem1__pause_frames_tx);
set_reset_data( gem1__frames_64b_tx, val_gem1__frames_64b_tx);
set_reset_data( gem1__frames_65to127b_tx, val_gem1__frames_65to127b_tx);
set_reset_data( gem1__frames_128to255b_tx, val_gem1__frames_128to255b_tx);
set_reset_data( gem1__frames_256to511b_tx, val_gem1__frames_256to511b_tx);
set_reset_data( gem1__frames_512to1023b_tx, val_gem1__frames_512to1023b_tx);
set_reset_data( gem1__frames_1024to1518b_tx, val_gem1__frames_1024to1518b_tx);
set_reset_data( gem1__frames_gt1518b_tx, val_gem1__frames_gt1518b_tx);
set_reset_data( gem1__tx_under_runs, val_gem1__tx_under_runs);
set_reset_data( gem1__single_collisn_frames, val_gem1__single_collisn_frames);
set_reset_data( gem1__multi_collisn_frames, val_gem1__multi_collisn_frames);
set_reset_data( gem1__excessive_collisns, val_gem1__excessive_collisns);
set_reset_data( gem1__late_collisns, val_gem1__late_collisns);
set_reset_data( gem1__deferred_tx_frames, val_gem1__deferred_tx_frames);
set_reset_data( gem1__carrier_sense_errs, val_gem1__carrier_sense_errs);
set_reset_data( gem1__octets_rx_bot, val_gem1__octets_rx_bot);
set_reset_data( gem1__octets_rx_top, val_gem1__octets_rx_top);
set_reset_data( gem1__frames_rx, val_gem1__frames_rx);
set_reset_data( gem1__bdcast_fames_rx, val_gem1__bdcast_fames_rx);
set_reset_data( gem1__multi_frames_rx, val_gem1__multi_frames_rx);
set_reset_data( gem1__pause_rx, val_gem1__pause_rx);
set_reset_data( gem1__frames_64b_rx, val_gem1__frames_64b_rx);
set_reset_data( gem1__frames_65to127b_rx, val_gem1__frames_65to127b_rx);
set_reset_data( gem1__frames_128to255b_rx, val_gem1__frames_128to255b_rx);
set_reset_data( gem1__frames_256to511b_rx, val_gem1__frames_256to511b_rx);
set_reset_data( gem1__frames_512to1023b_rx, val_gem1__frames_512to1023b_rx);
set_reset_data( gem1__frames_1024to1518b_rx, val_gem1__frames_1024to1518b_rx);
set_reset_data( gem1__frames_gt1518b_rx, val_gem1__frames_gt1518b_rx);
set_reset_data( gem1__undersz_rx, val_gem1__undersz_rx);
set_reset_data( gem1__oversz_rx, val_gem1__oversz_rx);
set_reset_data( gem1__jab_rx, val_gem1__jab_rx);
set_reset_data( gem1__fcs_errors, val_gem1__fcs_errors);
set_reset_data( gem1__length_field_errors, val_gem1__length_field_errors);
set_reset_data( gem1__rx_symbol_errors, val_gem1__rx_symbol_errors);
set_reset_data( gem1__align_errors, val_gem1__align_errors);
set_reset_data( gem1__rx_resource_errors, val_gem1__rx_resource_errors);
set_reset_data( gem1__rx_overrun_errors, val_gem1__rx_overrun_errors);
set_reset_data( gem1__ip_hdr_csum_errors, val_gem1__ip_hdr_csum_errors);
set_reset_data( gem1__tcp_csum_errors, val_gem1__tcp_csum_errors);
set_reset_data( gem1__udp_csum_errors, val_gem1__udp_csum_errors);
set_reset_data( gem1__timer_strobe_s, val_gem1__timer_strobe_s);
set_reset_data( gem1__timer_strobe_ns, val_gem1__timer_strobe_ns);
set_reset_data( gem1__timer_s, val_gem1__timer_s);
set_reset_data( gem1__timer_ns, val_gem1__timer_ns);
set_reset_data( gem1__timer_adjust, val_gem1__timer_adjust);
set_reset_data( gem1__timer_incr, val_gem1__timer_incr);
set_reset_data( gem1__ptp_tx_s, val_gem1__ptp_tx_s);
set_reset_data( gem1__ptp_tx_ns, val_gem1__ptp_tx_ns);
set_reset_data( gem1__ptp_rx_s, val_gem1__ptp_rx_s);
set_reset_data( gem1__ptp_rx_ns, val_gem1__ptp_rx_ns);
set_reset_data( gem1__ptp_peer_tx_s, val_gem1__ptp_peer_tx_s);
set_reset_data( gem1__ptp_peer_tx_ns, val_gem1__ptp_peer_tx_ns);
set_reset_data( gem1__ptp_peer_rx_s, val_gem1__ptp_peer_rx_s);
set_reset_data( gem1__ptp_peer_rx_ns, val_gem1__ptp_peer_rx_ns);
set_reset_data( gem1__pcs_ctrl, val_gem1__pcs_ctrl);
set_reset_data( gem1__pcs_status, val_gem1__pcs_status);
set_reset_data( gem1__pcs_upper_phy_id, val_gem1__pcs_upper_phy_id);
set_reset_data( gem1__pcs_lower_phy_id, val_gem1__pcs_lower_phy_id);
set_reset_data( gem1__pcs_autoneg_ad, val_gem1__pcs_autoneg_ad);
set_reset_data( gem1__pcs_autoneg_ability, val_gem1__pcs_autoneg_ability);
set_reset_data( gem1__pcs_autonec_exp, val_gem1__pcs_autonec_exp);
set_reset_data( gem1__pcs_autoneg_next_pg, val_gem1__pcs_autoneg_next_pg);
set_reset_data( gem1__pcs_autoneg_pnext_pg, val_gem1__pcs_autoneg_pnext_pg);
set_reset_data( gem1__pcs_extended_status, val_gem1__pcs_extended_status);
set_reset_data( gem1__design_cfg1, val_gem1__design_cfg1);
set_reset_data( gem1__design_cfg2, val_gem1__design_cfg2);
set_reset_data( gem1__design_cfg3, val_gem1__design_cfg3);
set_reset_data( gem1__design_cfg4, val_gem1__design_cfg4);
set_reset_data( gem1__design_cfg5, val_gem1__design_cfg5);
set_reset_data( gem1__design_cfg6, val_gem1__design_cfg6);
set_reset_data( gem1__design_cfg7, val_gem1__design_cfg7);
set_reset_data( gem1__isr_pq1, val_gem1__isr_pq1);
set_reset_data( gem1__isr_pq2, val_gem1__isr_pq2);
set_reset_data( gem1__isr_pq3, val_gem1__isr_pq3);
set_reset_data( gem1__isr_pq4, val_gem1__isr_pq4);
set_reset_data( gem1__isr_pq5, val_gem1__isr_pq5);
set_reset_data( gem1__isr_pq6, val_gem1__isr_pq6);
set_reset_data( gem1__isr_pq7, val_gem1__isr_pq7);
set_reset_data( gem1__tx_qbar_q1, val_gem1__tx_qbar_q1);
set_reset_data( gem1__tx_qbar_q2, val_gem1__tx_qbar_q2);
set_reset_data( gem1__tx_qbar_q3, val_gem1__tx_qbar_q3);
set_reset_data( gem1__tx_qbar_q4, val_gem1__tx_qbar_q4);
set_reset_data( gem1__tx_qbar_q5, val_gem1__tx_qbar_q5);
set_reset_data( gem1__tx_qbar_q6, val_gem1__tx_qbar_q6);
set_reset_data( gem1__tx_qbar_q7, val_gem1__tx_qbar_q7);
set_reset_data( gem1__rx_qbar_q1, val_gem1__rx_qbar_q1);
set_reset_data( gem1__rx_qbar_q2, val_gem1__rx_qbar_q2);
set_reset_data( gem1__rx_qbar_q3, val_gem1__rx_qbar_q3);
set_reset_data( gem1__rx_qbar_q4, val_gem1__rx_qbar_q4);
set_reset_data( gem1__rx_qbar_q5, val_gem1__rx_qbar_q5);
set_reset_data( gem1__rx_qbar_q6, val_gem1__rx_qbar_q6);
set_reset_data( gem1__rx_qbar_q7, val_gem1__rx_qbar_q7);
set_reset_data( gem1__rx_bufsz_q1, val_gem1__rx_bufsz_q1);
set_reset_data( gem1__rx_bufsz_q2, val_gem1__rx_bufsz_q2);
set_reset_data( gem1__rx_bufsz_q3, val_gem1__rx_bufsz_q3);
set_reset_data( gem1__rx_bufsz_q4, val_gem1__rx_bufsz_q4);
set_reset_data( gem1__rx_bufsz_q5, val_gem1__rx_bufsz_q5);
set_reset_data( gem1__rx_bufsz_q6, val_gem1__rx_bufsz_q6);
set_reset_data( gem1__rx_bufsz_q7, val_gem1__rx_bufsz_q7);
set_reset_data( gem1__screen_t1_r0, val_gem1__screen_t1_r0);
set_reset_data( gem1__screen_t1_r1, val_gem1__screen_t1_r1);
set_reset_data( gem1__screen_t1_r2, val_gem1__screen_t1_r2);
set_reset_data( gem1__screen_t1_r3, val_gem1__screen_t1_r3);
set_reset_data( gem1__screen_t1_r4, val_gem1__screen_t1_r4);
set_reset_data( gem1__screen_t1_r5, val_gem1__screen_t1_r5);
set_reset_data( gem1__screen_t1_r6, val_gem1__screen_t1_r6);
set_reset_data( gem1__screen_t1_r7, val_gem1__screen_t1_r7);
set_reset_data( gem1__screen_t1_r8, val_gem1__screen_t1_r8);
set_reset_data( gem1__screen_t1_r9, val_gem1__screen_t1_r9);
set_reset_data( gem1__screen_t1_r10, val_gem1__screen_t1_r10);
set_reset_data( gem1__screen_t1_r11, val_gem1__screen_t1_r11);
set_reset_data( gem1__screen_t1_r12, val_gem1__screen_t1_r12);
set_reset_data( gem1__screen_t1_r13, val_gem1__screen_t1_r13);
set_reset_data( gem1__screen_t1_r14, val_gem1__screen_t1_r14);
set_reset_data( gem1__screen_t1_r15, val_gem1__screen_t1_r15);
set_reset_data( gem1__screen_t2_r0, val_gem1__screen_t2_r0);
set_reset_data( gem1__screen_t2_r1, val_gem1__screen_t2_r1);
set_reset_data( gem1__screen_t2_r2, val_gem1__screen_t2_r2);
set_reset_data( gem1__screen_t2_r3, val_gem1__screen_t2_r3);
set_reset_data( gem1__screen_t2_r4, val_gem1__screen_t2_r4);
set_reset_data( gem1__screen_t2_r5, val_gem1__screen_t2_r5);
set_reset_data( gem1__screen_t2_r6, val_gem1__screen_t2_r6);
set_reset_data( gem1__screen_t2_r7, val_gem1__screen_t2_r7);
set_reset_data( gem1__screen_t2_r8, val_gem1__screen_t2_r8);
set_reset_data( gem1__screen_t2_r9, val_gem1__screen_t2_r9);
set_reset_data( gem1__screen_t2_r10, val_gem1__screen_t2_r10);
set_reset_data( gem1__screen_t2_r11, val_gem1__screen_t2_r11);
set_reset_data( gem1__screen_t2_r12, val_gem1__screen_t2_r12);
set_reset_data( gem1__screen_t2_r13, val_gem1__screen_t2_r13);
set_reset_data( gem1__screen_t2_r14, val_gem1__screen_t2_r14);
set_reset_data( gem1__screen_t2_r15, val_gem1__screen_t2_r15);
set_reset_data( gem1__intr_en_pq1, val_gem1__intr_en_pq1);
set_reset_data( gem1__intr_en_pq2, val_gem1__intr_en_pq2);
set_reset_data( gem1__intr_en_pq3, val_gem1__intr_en_pq3);
set_reset_data( gem1__intr_en_pq4, val_gem1__intr_en_pq4);
set_reset_data( gem1__intr_en_pq5, val_gem1__intr_en_pq5);
set_reset_data( gem1__intr_en_pq6, val_gem1__intr_en_pq6);
set_reset_data( gem1__intr_en_pq7, val_gem1__intr_en_pq7);
set_reset_data( gem1__intr_dis_pq1, val_gem1__intr_dis_pq1);
set_reset_data( gem1__intr_dis_pq2, val_gem1__intr_dis_pq2);
set_reset_data( gem1__intr_dis_pq3, val_gem1__intr_dis_pq3);
set_reset_data( gem1__intr_dis_pq4, val_gem1__intr_dis_pq4);
set_reset_data( gem1__intr_dis_pq5, val_gem1__intr_dis_pq5);
set_reset_data( gem1__intr_dis_pq6, val_gem1__intr_dis_pq6);
set_reset_data( gem1__intr_dis_pq7, val_gem1__intr_dis_pq7);
set_reset_data( gem1__intr_mask_pq1, val_gem1__intr_mask_pq1);
set_reset_data( gem1__intr_mask_pq2, val_gem1__intr_mask_pq2);
set_reset_data( gem1__intr_mask_pq3, val_gem1__intr_mask_pq3);
set_reset_data( gem1__intr_mask_pq4, val_gem1__intr_mask_pq4);
set_reset_data( gem1__intr_mask_pq5, val_gem1__intr_mask_pq5);
set_reset_data( gem1__intr_mask_pq6, val_gem1__intr_mask_pq6);
set_reset_data( gem1__intr_mask_pq7, val_gem1__intr_mask_pq7);

// ************************************************************
//   Module gpio gpio
//   doc version: 
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( gpio__MASK_DATA_0_LSW, val_gpio__MASK_DATA_0_LSW);
set_reset_data( gpio__MASK_DATA_0_MSW, val_gpio__MASK_DATA_0_MSW);
set_reset_data( gpio__MASK_DATA_1_LSW, val_gpio__MASK_DATA_1_LSW);
set_reset_data( gpio__MASK_DATA_1_MSW, val_gpio__MASK_DATA_1_MSW);
set_reset_data( gpio__MASK_DATA_2_LSW, val_gpio__MASK_DATA_2_LSW);
set_reset_data( gpio__MASK_DATA_2_MSW, val_gpio__MASK_DATA_2_MSW);
set_reset_data( gpio__MASK_DATA_3_LSW, val_gpio__MASK_DATA_3_LSW);
set_reset_data( gpio__MASK_DATA_3_MSW, val_gpio__MASK_DATA_3_MSW);
set_reset_data( gpio__DATA_0, val_gpio__DATA_0);
set_reset_data( gpio__DATA_1, val_gpio__DATA_1);
set_reset_data( gpio__DATA_2, val_gpio__DATA_2);
set_reset_data( gpio__DATA_3, val_gpio__DATA_3);
set_reset_data( gpio__DATA_0_RO, val_gpio__DATA_0_RO);
set_reset_data( gpio__DATA_1_RO, val_gpio__DATA_1_RO);
set_reset_data( gpio__DATA_2_RO, val_gpio__DATA_2_RO);
set_reset_data( gpio__DATA_3_RO, val_gpio__DATA_3_RO);
set_reset_data( gpio__BYPM_0, val_gpio__BYPM_0);
set_reset_data( gpio__DIRM_0, val_gpio__DIRM_0);
set_reset_data( gpio__OEN_0, val_gpio__OEN_0);
set_reset_data( gpio__INT_MASK_0, val_gpio__INT_MASK_0);
set_reset_data( gpio__INT_EN_0, val_gpio__INT_EN_0);
set_reset_data( gpio__INT_DIS_0, val_gpio__INT_DIS_0);
set_reset_data( gpio__INT_STAT_0, val_gpio__INT_STAT_0);
set_reset_data( gpio__INT_TYPE_0, val_gpio__INT_TYPE_0);
set_reset_data( gpio__INT_POLARITY_0, val_gpio__INT_POLARITY_0);
set_reset_data( gpio__INT_ANY_0, val_gpio__INT_ANY_0);
set_reset_data( gpio__BYPM_1, val_gpio__BYPM_1);
set_reset_data( gpio__DIRM_1, val_gpio__DIRM_1);
set_reset_data( gpio__OEN_1, val_gpio__OEN_1);
set_reset_data( gpio__INT_MASK_1, val_gpio__INT_MASK_1);
set_reset_data( gpio__INT_EN_1, val_gpio__INT_EN_1);
set_reset_data( gpio__INT_DIS_1, val_gpio__INT_DIS_1);
set_reset_data( gpio__INT_STAT_1, val_gpio__INT_STAT_1);
set_reset_data( gpio__INT_TYPE_1, val_gpio__INT_TYPE_1);
set_reset_data( gpio__INT_POLARITY_1, val_gpio__INT_POLARITY_1);
set_reset_data( gpio__INT_ANY_1, val_gpio__INT_ANY_1);
set_reset_data( gpio__BYPM_2, val_gpio__BYPM_2);
set_reset_data( gpio__DIRM_2, val_gpio__DIRM_2);
set_reset_data( gpio__OEN_2, val_gpio__OEN_2);
set_reset_data( gpio__INT_MASK_2, val_gpio__INT_MASK_2);
set_reset_data( gpio__INT_EN_2, val_gpio__INT_EN_2);
set_reset_data( gpio__INT_DIS_2, val_gpio__INT_DIS_2);
set_reset_data( gpio__INT_STAT_2, val_gpio__INT_STAT_2);
set_reset_data( gpio__INT_TYPE_2, val_gpio__INT_TYPE_2);
set_reset_data( gpio__INT_POLARITY_2, val_gpio__INT_POLARITY_2);
set_reset_data( gpio__INT_ANY_2, val_gpio__INT_ANY_2);
set_reset_data( gpio__BYPM_3, val_gpio__BYPM_3);
set_reset_data( gpio__DIRM_3, val_gpio__DIRM_3);
set_reset_data( gpio__OEN_3, val_gpio__OEN_3);
set_reset_data( gpio__INT_MASK_3, val_gpio__INT_MASK_3);
set_reset_data( gpio__INT_EN_3, val_gpio__INT_EN_3);
set_reset_data( gpio__INT_DIS_3, val_gpio__INT_DIS_3);
set_reset_data( gpio__INT_STAT_3, val_gpio__INT_STAT_3);
set_reset_data( gpio__INT_TYPE_3, val_gpio__INT_TYPE_3);
set_reset_data( gpio__INT_POLARITY_3, val_gpio__INT_POLARITY_3);
set_reset_data( gpio__INT_ANY_3, val_gpio__INT_ANY_3);

// ************************************************************
//   Module gpv_iou_switch gpv_iou_switch
//   doc version: 1.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( gpv_iou_switch__Remap, val_gpv_iou_switch__Remap);
set_reset_data( gpv_iou_switch__security2_sdio0, val_gpv_iou_switch__security2_sdio0);
set_reset_data( gpv_iou_switch__security3_sdio1, val_gpv_iou_switch__security3_sdio1);
set_reset_data( gpv_iou_switch__security4_qspi, val_gpv_iou_switch__security4_qspi);
set_reset_data( gpv_iou_switch__security5_miou, val_gpv_iou_switch__security5_miou);
set_reset_data( gpv_iou_switch__security6_apb_slaves, val_gpv_iou_switch__security6_apb_slaves);
set_reset_data( gpv_iou_switch__security7_smc, val_gpv_iou_switch__security7_smc);
set_reset_data( gpv_iou_switch__peripheral_id4, val_gpv_iou_switch__peripheral_id4);
set_reset_data( gpv_iou_switch__peripheral_id5, val_gpv_iou_switch__peripheral_id5);
set_reset_data( gpv_iou_switch__peripheral_id6, val_gpv_iou_switch__peripheral_id6);
set_reset_data( gpv_iou_switch__peripheral_id7, val_gpv_iou_switch__peripheral_id7);
set_reset_data( gpv_iou_switch__peripheral_id0, val_gpv_iou_switch__peripheral_id0);
set_reset_data( gpv_iou_switch__peripheral_id1, val_gpv_iou_switch__peripheral_id1);
set_reset_data( gpv_iou_switch__peripheral_id2, val_gpv_iou_switch__peripheral_id2);
set_reset_data( gpv_iou_switch__peripheral_id3, val_gpv_iou_switch__peripheral_id3);
set_reset_data( gpv_iou_switch__component_id0, val_gpv_iou_switch__component_id0);
set_reset_data( gpv_iou_switch__component_id1, val_gpv_iou_switch__component_id1);
set_reset_data( gpv_iou_switch__component_id2, val_gpv_iou_switch__component_id2);
set_reset_data( gpv_iou_switch__component_id3, val_gpv_iou_switch__component_id3);
set_reset_data( gpv_iou_switch__fn_mod_bm_iss_sdio0, val_gpv_iou_switch__fn_mod_bm_iss_sdio0);
set_reset_data( gpv_iou_switch__ahb_cntl_sdio0, val_gpv_iou_switch__ahb_cntl_sdio0);
set_reset_data( gpv_iou_switch__fn_mod_bm_iss_sdio1, val_gpv_iou_switch__fn_mod_bm_iss_sdio1);
set_reset_data( gpv_iou_switch__ahb_cntl_sdio1, val_gpv_iou_switch__ahb_cntl_sdio1);
set_reset_data( gpv_iou_switch__fn_mod_bm_iss_qspi, val_gpv_iou_switch__fn_mod_bm_iss_qspi);
set_reset_data( gpv_iou_switch__fn_mod_bm_iss_miou, val_gpv_iou_switch__fn_mod_bm_iss_miou);
set_reset_data( gpv_iou_switch__fn_mod_bm_iss_smc, val_gpv_iou_switch__fn_mod_bm_iss_smc);
set_reset_data( gpv_iou_switch__fn_mod_ahb_gem0, val_gpv_iou_switch__fn_mod_ahb_gem0);
set_reset_data( gpv_iou_switch__read_qos_gem0, val_gpv_iou_switch__read_qos_gem0);
set_reset_data( gpv_iou_switch__write_qos_gem0, val_gpv_iou_switch__write_qos_gem0);
set_reset_data( gpv_iou_switch__fn_mod_iss_gem0, val_gpv_iou_switch__fn_mod_iss_gem0);
set_reset_data( gpv_iou_switch__fn_mod_ahb_gem1, val_gpv_iou_switch__fn_mod_ahb_gem1);
set_reset_data( gpv_iou_switch__read_qos_gem1, val_gpv_iou_switch__read_qos_gem1);
set_reset_data( gpv_iou_switch__write_qos_gem1, val_gpv_iou_switch__write_qos_gem1);
set_reset_data( gpv_iou_switch__fn_mod_iss_gem1, val_gpv_iou_switch__fn_mod_iss_gem1);
set_reset_data( gpv_iou_switch__fn_mod_ahb_usb0, val_gpv_iou_switch__fn_mod_ahb_usb0);
set_reset_data( gpv_iou_switch__read_qos_usb0, val_gpv_iou_switch__read_qos_usb0);
set_reset_data( gpv_iou_switch__write_qos_usb0, val_gpv_iou_switch__write_qos_usb0);
set_reset_data( gpv_iou_switch__fn_mod_iss_usb0, val_gpv_iou_switch__fn_mod_iss_usb0);
set_reset_data( gpv_iou_switch__fn_mod_ahb_usb1, val_gpv_iou_switch__fn_mod_ahb_usb1);
set_reset_data( gpv_iou_switch__read_qos_usb1, val_gpv_iou_switch__read_qos_usb1);
set_reset_data( gpv_iou_switch__write_qos_usb1, val_gpv_iou_switch__write_qos_usb1);
set_reset_data( gpv_iou_switch__fn_mod_iss_usb1, val_gpv_iou_switch__fn_mod_iss_usb1);
set_reset_data( gpv_iou_switch__fn_mod_ahb_sdio0, val_gpv_iou_switch__fn_mod_ahb_sdio0);
set_reset_data( gpv_iou_switch__read_qos_sdio0, val_gpv_iou_switch__read_qos_sdio0);
set_reset_data( gpv_iou_switch__write_qos_sdio0, val_gpv_iou_switch__write_qos_sdio0);
set_reset_data( gpv_iou_switch__fn_mod_iss_sdio0, val_gpv_iou_switch__fn_mod_iss_sdio0);
set_reset_data( gpv_iou_switch__fn_mod_ahb_sdio1, val_gpv_iou_switch__fn_mod_ahb_sdio1);
set_reset_data( gpv_iou_switch__read_qos_sdio1, val_gpv_iou_switch__read_qos_sdio1);
set_reset_data( gpv_iou_switch__write_qos_sdio1, val_gpv_iou_switch__write_qos_sdio1);
set_reset_data( gpv_iou_switch__fn_mod_iss_sdio1, val_gpv_iou_switch__fn_mod_iss_sdio1);
set_reset_data( gpv_iou_switch__fn_mod_iss_siou, val_gpv_iou_switch__fn_mod_iss_siou);

// ************************************************************
//   Module gpv_qos301_cpu qos301
//   doc version: 1.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( gpv_qos301_cpu__qos_cntl, val_gpv_qos301_cpu__qos_cntl);
set_reset_data( gpv_qos301_cpu__max_ot, val_gpv_qos301_cpu__max_ot);
set_reset_data( gpv_qos301_cpu__max_comb_ot, val_gpv_qos301_cpu__max_comb_ot);
set_reset_data( gpv_qos301_cpu__aw_p, val_gpv_qos301_cpu__aw_p);
set_reset_data( gpv_qos301_cpu__aw_b, val_gpv_qos301_cpu__aw_b);
set_reset_data( gpv_qos301_cpu__aw_r, val_gpv_qos301_cpu__aw_r);
set_reset_data( gpv_qos301_cpu__ar_p, val_gpv_qos301_cpu__ar_p);
set_reset_data( gpv_qos301_cpu__ar_b, val_gpv_qos301_cpu__ar_b);
set_reset_data( gpv_qos301_cpu__ar_r, val_gpv_qos301_cpu__ar_r);

// ************************************************************
//   Module gpv_qos301_dmac qos301
//   doc version: 1.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( gpv_qos301_dmac__qos_cntl, val_gpv_qos301_dmac__qos_cntl);
set_reset_data( gpv_qos301_dmac__max_ot, val_gpv_qos301_dmac__max_ot);
set_reset_data( gpv_qos301_dmac__max_comb_ot, val_gpv_qos301_dmac__max_comb_ot);
set_reset_data( gpv_qos301_dmac__aw_p, val_gpv_qos301_dmac__aw_p);
set_reset_data( gpv_qos301_dmac__aw_b, val_gpv_qos301_dmac__aw_b);
set_reset_data( gpv_qos301_dmac__aw_r, val_gpv_qos301_dmac__aw_r);
set_reset_data( gpv_qos301_dmac__ar_p, val_gpv_qos301_dmac__ar_p);
set_reset_data( gpv_qos301_dmac__ar_b, val_gpv_qos301_dmac__ar_b);
set_reset_data( gpv_qos301_dmac__ar_r, val_gpv_qos301_dmac__ar_r);

// ************************************************************
//   Module gpv_qos301_iou qos301
//   doc version: 1.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( gpv_qos301_iou__qos_cntl, val_gpv_qos301_iou__qos_cntl);
set_reset_data( gpv_qos301_iou__max_ot, val_gpv_qos301_iou__max_ot);
set_reset_data( gpv_qos301_iou__max_comb_ot, val_gpv_qos301_iou__max_comb_ot);
set_reset_data( gpv_qos301_iou__aw_p, val_gpv_qos301_iou__aw_p);
set_reset_data( gpv_qos301_iou__aw_b, val_gpv_qos301_iou__aw_b);
set_reset_data( gpv_qos301_iou__aw_r, val_gpv_qos301_iou__aw_r);
set_reset_data( gpv_qos301_iou__ar_p, val_gpv_qos301_iou__ar_p);
set_reset_data( gpv_qos301_iou__ar_b, val_gpv_qos301_iou__ar_b);
set_reset_data( gpv_qos301_iou__ar_r, val_gpv_qos301_iou__ar_r);

// ************************************************************
//   Module gpv_trustzone nic301_addr_region_ctrl_registers
//   doc version: 1.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( gpv_trustzone__Remap, val_gpv_trustzone__Remap);
set_reset_data( gpv_trustzone__security_fssw_s0, val_gpv_trustzone__security_fssw_s0);
set_reset_data( gpv_trustzone__security_fssw_s1, val_gpv_trustzone__security_fssw_s1);
set_reset_data( gpv_trustzone__security_apb, val_gpv_trustzone__security_apb);

// ************************************************************
//   Module i2c0 IIC
//   doc version: 1.2
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( i2c0__Control_reg0, val_i2c0__Control_reg0);
set_reset_data( i2c0__Status_reg0, val_i2c0__Status_reg0);
set_reset_data( i2c0__I2C_address_reg0, val_i2c0__I2C_address_reg0);
set_reset_data( i2c0__I2C_data_reg0, val_i2c0__I2C_data_reg0);
set_reset_data( i2c0__Interrupt_status_reg0, val_i2c0__Interrupt_status_reg0);
set_reset_data( i2c0__Transfer_size_reg0, val_i2c0__Transfer_size_reg0);
set_reset_data( i2c0__Slave_mon_pause_reg0, val_i2c0__Slave_mon_pause_reg0);
set_reset_data( i2c0__Time_out_reg0, val_i2c0__Time_out_reg0);
set_reset_data( i2c0__Intrpt_mask_reg0, val_i2c0__Intrpt_mask_reg0);
set_reset_data( i2c0__Intrpt_enable_reg0, val_i2c0__Intrpt_enable_reg0);
set_reset_data( i2c0__Intrpt_disable_reg0, val_i2c0__Intrpt_disable_reg0);

// ************************************************************
//   Module i2c1 IIC
//   doc version: 1.2
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( i2c1__Control_reg0, val_i2c1__Control_reg0);
set_reset_data( i2c1__Status_reg0, val_i2c1__Status_reg0);
set_reset_data( i2c1__I2C_address_reg0, val_i2c1__I2C_address_reg0);
set_reset_data( i2c1__I2C_data_reg0, val_i2c1__I2C_data_reg0);
set_reset_data( i2c1__Interrupt_status_reg0, val_i2c1__Interrupt_status_reg0);
set_reset_data( i2c1__Transfer_size_reg0, val_i2c1__Transfer_size_reg0);
set_reset_data( i2c1__Slave_mon_pause_reg0, val_i2c1__Slave_mon_pause_reg0);
set_reset_data( i2c1__Time_out_reg0, val_i2c1__Time_out_reg0);
set_reset_data( i2c1__Intrpt_mask_reg0, val_i2c1__Intrpt_mask_reg0);
set_reset_data( i2c1__Intrpt_enable_reg0, val_i2c1__Intrpt_enable_reg0);
set_reset_data( i2c1__Intrpt_disable_reg0, val_i2c1__Intrpt_disable_reg0);

// ************************************************************
//   Module l2cache L2Cpl310
//   doc version: 1.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( l2cache__reg0_cache_id, val_l2cache__reg0_cache_id);
set_reset_data( l2cache__reg0_cache_type, val_l2cache__reg0_cache_type);
set_reset_data( l2cache__reg1_control, val_l2cache__reg1_control);
set_reset_data( l2cache__reg1_aux_control, val_l2cache__reg1_aux_control);
set_reset_data( l2cache__reg1_tag_ram_control, val_l2cache__reg1_tag_ram_control);
set_reset_data( l2cache__reg1_data_ram_control, val_l2cache__reg1_data_ram_control);
set_reset_data( l2cache__reg2_ev_counter_ctrl, val_l2cache__reg2_ev_counter_ctrl);
set_reset_data( l2cache__reg2_ev_counter1_cfg, val_l2cache__reg2_ev_counter1_cfg);
set_reset_data( l2cache__reg2_ev_counter0_cfg, val_l2cache__reg2_ev_counter0_cfg);
set_reset_data( l2cache__reg2_ev_counter1, val_l2cache__reg2_ev_counter1);
set_reset_data( l2cache__reg2_ev_counter0, val_l2cache__reg2_ev_counter0);
set_reset_data( l2cache__reg2_int_mask, val_l2cache__reg2_int_mask);
set_reset_data( l2cache__reg2_int_mask_status, val_l2cache__reg2_int_mask_status);
set_reset_data( l2cache__reg2_int_raw_status, val_l2cache__reg2_int_raw_status);
set_reset_data( l2cache__reg2_int_clear, val_l2cache__reg2_int_clear);
set_reset_data( l2cache__reg7_cache_sync, val_l2cache__reg7_cache_sync);
set_reset_data( l2cache__reg7_inv_pa, val_l2cache__reg7_inv_pa);
set_reset_data( l2cache__reg7_inv_way, val_l2cache__reg7_inv_way);
set_reset_data( l2cache__reg7_clean_pa, val_l2cache__reg7_clean_pa);
set_reset_data( l2cache__reg7_clean_index, val_l2cache__reg7_clean_index);
set_reset_data( l2cache__reg7_clean_way, val_l2cache__reg7_clean_way);
set_reset_data( l2cache__reg7_clean_inv_pa, val_l2cache__reg7_clean_inv_pa);
set_reset_data( l2cache__reg7_clean_inv_index, val_l2cache__reg7_clean_inv_index);
set_reset_data( l2cache__reg7_clean_inv_way, val_l2cache__reg7_clean_inv_way);
set_reset_data( l2cache__reg9_d_lockdown0, val_l2cache__reg9_d_lockdown0);
set_reset_data( l2cache__reg9_i_lockdown0, val_l2cache__reg9_i_lockdown0);
set_reset_data( l2cache__reg9_d_lockdown1, val_l2cache__reg9_d_lockdown1);
set_reset_data( l2cache__reg9_i_lockdown1, val_l2cache__reg9_i_lockdown1);
set_reset_data( l2cache__reg9_d_lockdown2, val_l2cache__reg9_d_lockdown2);
set_reset_data( l2cache__reg9_i_lockdown2, val_l2cache__reg9_i_lockdown2);
set_reset_data( l2cache__reg9_d_lockdown3, val_l2cache__reg9_d_lockdown3);
set_reset_data( l2cache__reg9_i_lockdown3, val_l2cache__reg9_i_lockdown3);
set_reset_data( l2cache__reg9_d_lockdown4, val_l2cache__reg9_d_lockdown4);
set_reset_data( l2cache__reg9_i_lockdown4, val_l2cache__reg9_i_lockdown4);
set_reset_data( l2cache__reg9_d_lockdown5, val_l2cache__reg9_d_lockdown5);
set_reset_data( l2cache__reg9_i_lockdown5, val_l2cache__reg9_i_lockdown5);
set_reset_data( l2cache__reg9_d_lockdown6, val_l2cache__reg9_d_lockdown6);
set_reset_data( l2cache__reg9_i_lockdown6, val_l2cache__reg9_i_lockdown6);
set_reset_data( l2cache__reg9_d_lockdown7, val_l2cache__reg9_d_lockdown7);
set_reset_data( l2cache__reg9_i_lockdown7, val_l2cache__reg9_i_lockdown7);
set_reset_data( l2cache__reg9_lock_line_en, val_l2cache__reg9_lock_line_en);
set_reset_data( l2cache__reg9_unlock_way, val_l2cache__reg9_unlock_way);
set_reset_data( l2cache__reg12_addr_filtering_start, val_l2cache__reg12_addr_filtering_start);
set_reset_data( l2cache__reg12_addr_filtering_end, val_l2cache__reg12_addr_filtering_end);
set_reset_data( l2cache__reg15_debug_ctrl, val_l2cache__reg15_debug_ctrl);
set_reset_data( l2cache__reg15_prefetch_ctrl, val_l2cache__reg15_prefetch_ctrl);
set_reset_data( l2cache__reg15_power_ctrl, val_l2cache__reg15_power_ctrl);

// ************************************************************
//   Module mpcore mpcore
//   doc version: 1.3
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( mpcore__SCU_CONTROL_REGISTER, val_mpcore__SCU_CONTROL_REGISTER);
set_reset_data( mpcore__SCU_CONFIGURATION_REGISTER, val_mpcore__SCU_CONFIGURATION_REGISTER);
set_reset_data( mpcore__SCU_CPU_Power_Status_Register, val_mpcore__SCU_CPU_Power_Status_Register);
set_reset_data( mpcore__SCU_Invalidate_All_Registers_in_Secure_State, val_mpcore__SCU_Invalidate_All_Registers_in_Secure_State);
set_reset_data( mpcore__Filtering_Start_Address_Register, val_mpcore__Filtering_Start_Address_Register);
set_reset_data( mpcore__Filtering_End_Address_Register, val_mpcore__Filtering_End_Address_Register);
set_reset_data( mpcore__SCU_Access_Control_Register_SAC, val_mpcore__SCU_Access_Control_Register_SAC);
set_reset_data( mpcore__SCU_Non_secure_Access_Control_Register, val_mpcore__SCU_Non_secure_Access_Control_Register);
set_reset_data( mpcore__ICCICR, val_mpcore__ICCICR);
set_reset_data( mpcore__ICCPMR, val_mpcore__ICCPMR);
set_reset_data( mpcore__ICCBPR, val_mpcore__ICCBPR);
set_reset_data( mpcore__ICCIAR, val_mpcore__ICCIAR);
set_reset_data( mpcore__ICCEOIR, val_mpcore__ICCEOIR);
set_reset_data( mpcore__ICCRPR, val_mpcore__ICCRPR);
set_reset_data( mpcore__ICCHPIR, val_mpcore__ICCHPIR);
set_reset_data( mpcore__ICCABPR, val_mpcore__ICCABPR);
set_reset_data( mpcore__ICCIDR, val_mpcore__ICCIDR);
set_reset_data( mpcore__Global_Timer_Counter_Register0, val_mpcore__Global_Timer_Counter_Register0);
set_reset_data( mpcore__Global_Timer_Counter_Register1, val_mpcore__Global_Timer_Counter_Register1);
set_reset_data( mpcore__Global_Timer_Control_Register, val_mpcore__Global_Timer_Control_Register);
set_reset_data( mpcore__Global_Timer_Interrupt_Status_Register, val_mpcore__Global_Timer_Interrupt_Status_Register);
set_reset_data( mpcore__Comparator_Value_Register0, val_mpcore__Comparator_Value_Register0);
set_reset_data( mpcore__Comparator_Value_Register1, val_mpcore__Comparator_Value_Register1);
set_reset_data( mpcore__Auto_increment_Register, val_mpcore__Auto_increment_Register);
set_reset_data( mpcore__Private_Timer_Load_Register, val_mpcore__Private_Timer_Load_Register);
set_reset_data( mpcore__Private_Timer_Counter_Register, val_mpcore__Private_Timer_Counter_Register);
set_reset_data( mpcore__Private_Timer_Control_Register, val_mpcore__Private_Timer_Control_Register);
set_reset_data( mpcore__Private_Timer_Interrupt_Status_Register, val_mpcore__Private_Timer_Interrupt_Status_Register);
set_reset_data( mpcore__Watchdog_Load_Register, val_mpcore__Watchdog_Load_Register);
set_reset_data( mpcore__Watchdog_Counter_Register, val_mpcore__Watchdog_Counter_Register);
set_reset_data( mpcore__Watchdog_Control_Register, val_mpcore__Watchdog_Control_Register);
set_reset_data( mpcore__Watchdog_Interrupt_Status_Register, val_mpcore__Watchdog_Interrupt_Status_Register);
set_reset_data( mpcore__Watchdog_Reset_Status_Register, val_mpcore__Watchdog_Reset_Status_Register);
set_reset_data( mpcore__Watchdog_Disable_Register, val_mpcore__Watchdog_Disable_Register);
set_reset_data( mpcore__ICDDCR, val_mpcore__ICDDCR);
set_reset_data( mpcore__ICDICTR, val_mpcore__ICDICTR);
set_reset_data( mpcore__ICDIIDR, val_mpcore__ICDIIDR);
set_reset_data( mpcore__ICDISR0, val_mpcore__ICDISR0);
set_reset_data( mpcore__ICDISR1, val_mpcore__ICDISR1);
set_reset_data( mpcore__ICDISR2, val_mpcore__ICDISR2);
set_reset_data( mpcore__ICDISER0, val_mpcore__ICDISER0);
set_reset_data( mpcore__ICDISER1, val_mpcore__ICDISER1);
set_reset_data( mpcore__ICDISER2, val_mpcore__ICDISER2);
set_reset_data( mpcore__ICDICER0, val_mpcore__ICDICER0);
set_reset_data( mpcore__ICDICER1, val_mpcore__ICDICER1);
set_reset_data( mpcore__ICDICER2, val_mpcore__ICDICER2);
set_reset_data( mpcore__ICDISPR0, val_mpcore__ICDISPR0);
set_reset_data( mpcore__ICDISPR1, val_mpcore__ICDISPR1);
set_reset_data( mpcore__ICDISPR2, val_mpcore__ICDISPR2);
set_reset_data( mpcore__ICDICPR0, val_mpcore__ICDICPR0);
set_reset_data( mpcore__ICDICPR1, val_mpcore__ICDICPR1);
set_reset_data( mpcore__ICDICPR2, val_mpcore__ICDICPR2);
set_reset_data( mpcore__ICDABR0, val_mpcore__ICDABR0);
set_reset_data( mpcore__ICDABR1, val_mpcore__ICDABR1);
set_reset_data( mpcore__ICDABR2, val_mpcore__ICDABR2);
set_reset_data( mpcore__ICDIPR0, val_mpcore__ICDIPR0);
set_reset_data( mpcore__ICDIPR1, val_mpcore__ICDIPR1);
set_reset_data( mpcore__ICDIPR2, val_mpcore__ICDIPR2);
set_reset_data( mpcore__ICDIPR3, val_mpcore__ICDIPR3);
set_reset_data( mpcore__ICDIPR4, val_mpcore__ICDIPR4);
set_reset_data( mpcore__ICDIPR5, val_mpcore__ICDIPR5);
set_reset_data( mpcore__ICDIPR6, val_mpcore__ICDIPR6);
set_reset_data( mpcore__ICDIPR7, val_mpcore__ICDIPR7);
set_reset_data( mpcore__ICDIPR8, val_mpcore__ICDIPR8);
set_reset_data( mpcore__ICDIPR9, val_mpcore__ICDIPR9);
set_reset_data( mpcore__ICDIPR10, val_mpcore__ICDIPR10);
set_reset_data( mpcore__ICDIPR11, val_mpcore__ICDIPR11);
set_reset_data( mpcore__ICDIPR12, val_mpcore__ICDIPR12);
set_reset_data( mpcore__ICDIPR13, val_mpcore__ICDIPR13);
set_reset_data( mpcore__ICDIPR14, val_mpcore__ICDIPR14);
set_reset_data( mpcore__ICDIPR15, val_mpcore__ICDIPR15);
set_reset_data( mpcore__ICDIPR16, val_mpcore__ICDIPR16);
set_reset_data( mpcore__ICDIPR17, val_mpcore__ICDIPR17);
set_reset_data( mpcore__ICDIPR18, val_mpcore__ICDIPR18);
set_reset_data( mpcore__ICDIPR19, val_mpcore__ICDIPR19);
set_reset_data( mpcore__ICDIPR20, val_mpcore__ICDIPR20);
set_reset_data( mpcore__ICDIPR21, val_mpcore__ICDIPR21);
set_reset_data( mpcore__ICDIPR22, val_mpcore__ICDIPR22);
set_reset_data( mpcore__ICDIPR23, val_mpcore__ICDIPR23);
set_reset_data( mpcore__ICDIPTR0, val_mpcore__ICDIPTR0);
set_reset_data( mpcore__ICDIPTR1, val_mpcore__ICDIPTR1);
set_reset_data( mpcore__ICDIPTR2, val_mpcore__ICDIPTR2);
set_reset_data( mpcore__ICDIPTR3, val_mpcore__ICDIPTR3);
set_reset_data( mpcore__ICDIPTR4, val_mpcore__ICDIPTR4);
set_reset_data( mpcore__ICDIPTR5, val_mpcore__ICDIPTR5);
set_reset_data( mpcore__ICDIPTR6, val_mpcore__ICDIPTR6);
set_reset_data( mpcore__ICDIPTR7, val_mpcore__ICDIPTR7);
set_reset_data( mpcore__ICDIPTR8, val_mpcore__ICDIPTR8);
set_reset_data( mpcore__ICDIPTR9, val_mpcore__ICDIPTR9);
set_reset_data( mpcore__ICDIPTR10, val_mpcore__ICDIPTR10);
set_reset_data( mpcore__ICDIPTR11, val_mpcore__ICDIPTR11);
set_reset_data( mpcore__ICDIPTR12, val_mpcore__ICDIPTR12);
set_reset_data( mpcore__ICDIPTR13, val_mpcore__ICDIPTR13);
set_reset_data( mpcore__ICDIPTR14, val_mpcore__ICDIPTR14);
set_reset_data( mpcore__ICDIPTR15, val_mpcore__ICDIPTR15);
set_reset_data( mpcore__ICDIPTR16, val_mpcore__ICDIPTR16);
set_reset_data( mpcore__ICDIPTR17, val_mpcore__ICDIPTR17);
set_reset_data( mpcore__ICDIPTR18, val_mpcore__ICDIPTR18);
set_reset_data( mpcore__ICDIPTR19, val_mpcore__ICDIPTR19);
set_reset_data( mpcore__ICDIPTR20, val_mpcore__ICDIPTR20);
set_reset_data( mpcore__ICDIPTR21, val_mpcore__ICDIPTR21);
set_reset_data( mpcore__ICDIPTR22, val_mpcore__ICDIPTR22);
set_reset_data( mpcore__ICDIPTR23, val_mpcore__ICDIPTR23);
set_reset_data( mpcore__ICDICFR0, val_mpcore__ICDICFR0);
set_reset_data( mpcore__ICDICFR1, val_mpcore__ICDICFR1);
set_reset_data( mpcore__ICDICFR2, val_mpcore__ICDICFR2);
set_reset_data( mpcore__ICDICFR3, val_mpcore__ICDICFR3);
set_reset_data( mpcore__ICDICFR4, val_mpcore__ICDICFR4);
set_reset_data( mpcore__ICDICFR5, val_mpcore__ICDICFR5);
set_reset_data( mpcore__ppi_status, val_mpcore__ppi_status);
set_reset_data( mpcore__spi_status_0, val_mpcore__spi_status_0);
set_reset_data( mpcore__spi_status_1, val_mpcore__spi_status_1);
set_reset_data( mpcore__ICDSGIR, val_mpcore__ICDSGIR);
set_reset_data( mpcore__ICPIDR4, val_mpcore__ICPIDR4);
set_reset_data( mpcore__ICPIDR5, val_mpcore__ICPIDR5);
set_reset_data( mpcore__ICPIDR6, val_mpcore__ICPIDR6);
set_reset_data( mpcore__ICPIDR7, val_mpcore__ICPIDR7);
set_reset_data( mpcore__ICPIDR0, val_mpcore__ICPIDR0);
set_reset_data( mpcore__ICPIDR1, val_mpcore__ICPIDR1);
set_reset_data( mpcore__ICPIDR2, val_mpcore__ICPIDR2);
set_reset_data( mpcore__ICPIDR3, val_mpcore__ICPIDR3);
set_reset_data( mpcore__ICCIDR0, val_mpcore__ICCIDR0);
set_reset_data( mpcore__ICCIDR1, val_mpcore__ICCIDR1);
set_reset_data( mpcore__ICCIDR2, val_mpcore__ICCIDR2);
set_reset_data( mpcore__ICCIDR3, val_mpcore__ICCIDR3);

// ************************************************************
//   Module ocm ocm
//   doc version: 1.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( ocm__OCM_PARITY_CTRL, val_ocm__OCM_PARITY_CTRL);
set_reset_data( ocm__OCM_PARITY_ERRADDRESS, val_ocm__OCM_PARITY_ERRADDRESS);
set_reset_data( ocm__OCM_IRQ_STS, val_ocm__OCM_IRQ_STS);
set_reset_data( ocm__OCM_CONTROL, val_ocm__OCM_CONTROL);

// ************************************************************
//   Module qspi qspi
//   doc version: 0.8, based on 11/01/10 Linear Quad-SPI Controller
/// Design Specification document
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( qspi__Config_reg, val_qspi__Config_reg);
set_reset_data( qspi__Intr_status_REG, val_qspi__Intr_status_REG);
set_reset_data( qspi__Intrpt_en_REG, val_qspi__Intrpt_en_REG);
set_reset_data( qspi__Intrpt_dis_REG, val_qspi__Intrpt_dis_REG);
set_reset_data( qspi__Intrpt_mask_REG, val_qspi__Intrpt_mask_REG);
set_reset_data( qspi__En_REG, val_qspi__En_REG);
set_reset_data( qspi__Delay_REG, val_qspi__Delay_REG);
set_reset_data( qspi__TXD0, val_qspi__TXD0);
set_reset_data( qspi__Rx_data_REG, val_qspi__Rx_data_REG);
set_reset_data( qspi__Slave_Idle_count_REG, val_qspi__Slave_Idle_count_REG);
set_reset_data( qspi__TX_thres_REG, val_qspi__TX_thres_REG);
set_reset_data( qspi__RX_thres_REG, val_qspi__RX_thres_REG);
set_reset_data( qspi__GPIO, val_qspi__GPIO);
set_reset_data( qspi__LPBK_DLY_ADJ, val_qspi__LPBK_DLY_ADJ);
set_reset_data( qspi__TXD1, val_qspi__TXD1);
set_reset_data( qspi__TXD2, val_qspi__TXD2);
set_reset_data( qspi__TXD3, val_qspi__TXD3);
set_reset_data( qspi__LQSPI_CFG, val_qspi__LQSPI_CFG);
set_reset_data( qspi__LQSPI_STS, val_qspi__LQSPI_STS);
set_reset_data( qspi__MOD_ID, val_qspi__MOD_ID);

// ************************************************************
//   Module sd0 sdio
//   doc version: 4.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( sd0__SDMA_system_address_register, val_sd0__SDMA_system_address_register);
set_reset_data( sd0__Block_Size_Block_Count, val_sd0__Block_Size_Block_Count);
set_reset_data( sd0__Argument, val_sd0__Argument);
set_reset_data( sd0__Transfer_Mode_Command, val_sd0__Transfer_Mode_Command);
set_reset_data( sd0__Response0, val_sd0__Response0);
set_reset_data( sd0__Response1, val_sd0__Response1);
set_reset_data( sd0__Response2, val_sd0__Response2);
set_reset_data( sd0__Response3, val_sd0__Response3);
set_reset_data( sd0__Buffer_Data_Port, val_sd0__Buffer_Data_Port);
set_reset_data( sd0__Present_State, val_sd0__Present_State);
set_reset_data( sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control, val_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control);
set_reset_data( sd0__Clock_Control_Timeout_control_Software_reset, val_sd0__Clock_Control_Timeout_control_Software_reset);
set_reset_data( sd0__Normal_interrupt_status_Error_interrupt_status, val_sd0__Normal_interrupt_status_Error_interrupt_status);
set_reset_data( sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable, val_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable);
set_reset_data( sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable, val_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable);
set_reset_data( sd0__Auto_CMD12_error_status, val_sd0__Auto_CMD12_error_status);
set_reset_data( sd0__Capabilities, val_sd0__Capabilities);
set_reset_data( sd0__Maximum_current_capabilities, val_sd0__Maximum_current_capabilities);
set_reset_data( sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status, val_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status);
set_reset_data( sd0__ADMA_error_status, val_sd0__ADMA_error_status);
set_reset_data( sd0__ADMA_system_address, val_sd0__ADMA_system_address);
set_reset_data( sd0__Boot_Timeout_control, val_sd0__Boot_Timeout_control);
set_reset_data( sd0__Debug_Selection, val_sd0__Debug_Selection);
set_reset_data( sd0__SPI_interrupt_support, val_sd0__SPI_interrupt_support);
set_reset_data( sd0__Slot_interrupt_status_Host_controller_version, val_sd0__Slot_interrupt_status_Host_controller_version);

// ************************************************************
//   Module sd1 sdio
//   doc version: 4.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( sd1__SDMA_system_address_register, val_sd1__SDMA_system_address_register);
set_reset_data( sd1__Block_Size_Block_Count, val_sd1__Block_Size_Block_Count);
set_reset_data( sd1__Argument, val_sd1__Argument);
set_reset_data( sd1__Transfer_Mode_Command, val_sd1__Transfer_Mode_Command);
set_reset_data( sd1__Response0, val_sd1__Response0);
set_reset_data( sd1__Response1, val_sd1__Response1);
set_reset_data( sd1__Response2, val_sd1__Response2);
set_reset_data( sd1__Response3, val_sd1__Response3);
set_reset_data( sd1__Buffer_Data_Port, val_sd1__Buffer_Data_Port);
set_reset_data( sd1__Present_State, val_sd1__Present_State);
set_reset_data( sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control, val_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control);
set_reset_data( sd1__Clock_Control_Timeout_control_Software_reset, val_sd1__Clock_Control_Timeout_control_Software_reset);
set_reset_data( sd1__Normal_interrupt_status_Error_interrupt_status, val_sd1__Normal_interrupt_status_Error_interrupt_status);
set_reset_data( sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable, val_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable);
set_reset_data( sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable, val_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable);
set_reset_data( sd1__Auto_CMD12_error_status, val_sd1__Auto_CMD12_error_status);
set_reset_data( sd1__Capabilities, val_sd1__Capabilities);
set_reset_data( sd1__Maximum_current_capabilities, val_sd1__Maximum_current_capabilities);
set_reset_data( sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status, val_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status);
set_reset_data( sd1__ADMA_error_status, val_sd1__ADMA_error_status);
set_reset_data( sd1__ADMA_system_address, val_sd1__ADMA_system_address);
set_reset_data( sd1__Boot_Timeout_control, val_sd1__Boot_Timeout_control);
set_reset_data( sd1__Debug_Selection, val_sd1__Debug_Selection);
set_reset_data( sd1__SPI_interrupt_support, val_sd1__SPI_interrupt_support);
set_reset_data( sd1__Slot_interrupt_status_Host_controller_version, val_sd1__Slot_interrupt_status_Host_controller_version);

// ************************************************************
//   Module slcr slcr
//   doc version: 1.3, based on 11/18/2010 SLCR_spec.doc
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( slcr__SCL, val_slcr__SCL);
set_reset_data( slcr__SLCR_LOCK, val_slcr__SLCR_LOCK);
set_reset_data( slcr__SLCR_UNLOCK, val_slcr__SLCR_UNLOCK);
set_reset_data( slcr__SLCR_LOCKSTA, val_slcr__SLCR_LOCKSTA);
set_reset_data( slcr__ARM_PLL_CTRL, val_slcr__ARM_PLL_CTRL);
set_reset_data( slcr__DDR_PLL_CTRL, val_slcr__DDR_PLL_CTRL);
set_reset_data( slcr__IO_PLL_CTRL, val_slcr__IO_PLL_CTRL);
set_reset_data( slcr__PLL_STATUS, val_slcr__PLL_STATUS);
set_reset_data( slcr__ARM_PLL_CFG, val_slcr__ARM_PLL_CFG);
set_reset_data( slcr__DDR_PLL_CFG, val_slcr__DDR_PLL_CFG);
set_reset_data( slcr__IO_PLL_CFG, val_slcr__IO_PLL_CFG);
set_reset_data( slcr__PLL_BG_CTRL, val_slcr__PLL_BG_CTRL);
set_reset_data( slcr__ARM_CLK_CTRL, val_slcr__ARM_CLK_CTRL);
set_reset_data( slcr__DDR_CLK_CTRL, val_slcr__DDR_CLK_CTRL);
set_reset_data( slcr__DCI_CLK_CTRL, val_slcr__DCI_CLK_CTRL);
set_reset_data( slcr__APER_CLK_CTRL, val_slcr__APER_CLK_CTRL);
set_reset_data( slcr__USB0_CLK_CTRL, val_slcr__USB0_CLK_CTRL);
set_reset_data( slcr__USB1_CLK_CTRL, val_slcr__USB1_CLK_CTRL);
set_reset_data( slcr__GEM0_RCLK_CTRL, val_slcr__GEM0_RCLK_CTRL);
set_reset_data( slcr__GEM1_RCLK_CTRL, val_slcr__GEM1_RCLK_CTRL);
set_reset_data( slcr__GEM0_CLK_CTRL, val_slcr__GEM0_CLK_CTRL);
set_reset_data( slcr__GEM1_CLK_CTRL, val_slcr__GEM1_CLK_CTRL);
set_reset_data( slcr__SMC_CLK_CTRL, val_slcr__SMC_CLK_CTRL);
set_reset_data( slcr__LQSPI_CLK_CTRL, val_slcr__LQSPI_CLK_CTRL);
set_reset_data( slcr__SDIO_CLK_CTRL, val_slcr__SDIO_CLK_CTRL);
set_reset_data( slcr__UART_CLK_CTRL, val_slcr__UART_CLK_CTRL);
set_reset_data( slcr__SPI_CLK_CTRL, val_slcr__SPI_CLK_CTRL);
set_reset_data( slcr__CAN_CLK_CTRL, val_slcr__CAN_CLK_CTRL);
set_reset_data( slcr__CAN_MIOCLK_CTRL, val_slcr__CAN_MIOCLK_CTRL);
set_reset_data( slcr__DBG_CLK_CTRL, val_slcr__DBG_CLK_CTRL);
set_reset_data( slcr__PCAP_CLK_CTRL, val_slcr__PCAP_CLK_CTRL);
set_reset_data( slcr__TOPSW_CLK_CTRL, val_slcr__TOPSW_CLK_CTRL);
set_reset_data( slcr__FPGA0_CLK_CTRL, val_slcr__FPGA0_CLK_CTRL);
set_reset_data( slcr__FPGA0_THR_CTRL, val_slcr__FPGA0_THR_CTRL);
set_reset_data( slcr__FPGA0_THR_CNT, val_slcr__FPGA0_THR_CNT);
set_reset_data( slcr__FPGA0_THR_STA, val_slcr__FPGA0_THR_STA);
set_reset_data( slcr__FPGA1_CLK_CTRL, val_slcr__FPGA1_CLK_CTRL);
set_reset_data( slcr__FPGA1_THR_CTRL, val_slcr__FPGA1_THR_CTRL);
set_reset_data( slcr__FPGA1_THR_CNT, val_slcr__FPGA1_THR_CNT);
set_reset_data( slcr__FPGA1_THR_STA, val_slcr__FPGA1_THR_STA);
set_reset_data( slcr__FPGA2_CLK_CTRL, val_slcr__FPGA2_CLK_CTRL);
set_reset_data( slcr__FPGA2_THR_CTRL, val_slcr__FPGA2_THR_CTRL);
set_reset_data( slcr__FPGA2_THR_CNT, val_slcr__FPGA2_THR_CNT);
set_reset_data( slcr__FPGA2_THR_STA, val_slcr__FPGA2_THR_STA);
set_reset_data( slcr__FPGA3_CLK_CTRL, val_slcr__FPGA3_CLK_CTRL);
set_reset_data( slcr__FPGA3_THR_CTRL, val_slcr__FPGA3_THR_CTRL);
set_reset_data( slcr__FPGA3_THR_CNT, val_slcr__FPGA3_THR_CNT);
set_reset_data( slcr__FPGA3_THR_STA, val_slcr__FPGA3_THR_STA);
set_reset_data( slcr__SRST_UART_CTRL, val_slcr__SRST_UART_CTRL);
set_reset_data( slcr__BANDGAP_TRIM, val_slcr__BANDGAP_TRIM);
set_reset_data( slcr__CC_TEST, val_slcr__CC_TEST);
set_reset_data( slcr__PLL_PREDIVISOR, val_slcr__PLL_PREDIVISOR);
set_reset_data( slcr__CLK_621_TRUE, val_slcr__CLK_621_TRUE);
set_reset_data( slcr__PICTURE_DBG, val_slcr__PICTURE_DBG);
set_reset_data( slcr__PICTURE_DBG_UCNT, val_slcr__PICTURE_DBG_UCNT);
set_reset_data( slcr__PICTURE_DBG_LCNT, val_slcr__PICTURE_DBG_LCNT);
set_reset_data( slcr__PSS_RST_CTRL, val_slcr__PSS_RST_CTRL);
set_reset_data( slcr__DDR_RST_CTRL, val_slcr__DDR_RST_CTRL);
set_reset_data( slcr__TOPSW_RST_CTRL, val_slcr__TOPSW_RST_CTRL);
set_reset_data( slcr__DMAC_RST_CTRL, val_slcr__DMAC_RST_CTRL);
set_reset_data( slcr__USB_RST_CTRL, val_slcr__USB_RST_CTRL);
set_reset_data( slcr__GEM_RST_CTRL, val_slcr__GEM_RST_CTRL);
set_reset_data( slcr__SDIO_RST_CTRL, val_slcr__SDIO_RST_CTRL);
set_reset_data( slcr__SPI_RST_CTRL, val_slcr__SPI_RST_CTRL);
set_reset_data( slcr__CAN_RST_CTRL, val_slcr__CAN_RST_CTRL);
set_reset_data( slcr__I2C_RST_CTRL, val_slcr__I2C_RST_CTRL);
set_reset_data( slcr__UART_RST_CTRL, val_slcr__UART_RST_CTRL);
set_reset_data( slcr__GPIO_RST_CTRL, val_slcr__GPIO_RST_CTRL);
set_reset_data( slcr__LQSPI_RST_CTRL, val_slcr__LQSPI_RST_CTRL);
set_reset_data( slcr__SMC_RST_CTRL, val_slcr__SMC_RST_CTRL);
set_reset_data( slcr__OCM_RST_CTRL, val_slcr__OCM_RST_CTRL);
set_reset_data( slcr__DEVCI_RST_CTRL, val_slcr__DEVCI_RST_CTRL);
set_reset_data( slcr__FPGA_RST_CTRL, val_slcr__FPGA_RST_CTRL);
set_reset_data( slcr__A9_CPU_RST_CTRL, val_slcr__A9_CPU_RST_CTRL);
set_reset_data( slcr__RS_AWDT_CTRL, val_slcr__RS_AWDT_CTRL);
set_reset_data( slcr__RST_REASON, val_slcr__RST_REASON);
set_reset_data( slcr__RST_REASON_CLR, val_slcr__RST_REASON_CLR);
set_reset_data( slcr__REBOOT_STATUS, val_slcr__REBOOT_STATUS);
set_reset_data( slcr__BOOT_MODE, val_slcr__BOOT_MODE);
set_reset_data( slcr__APU_CTRL, val_slcr__APU_CTRL);
set_reset_data( slcr__WDT_CLK_SEL, val_slcr__WDT_CLK_SEL);
set_reset_data( slcr__TZ_OCM_RAM0, val_slcr__TZ_OCM_RAM0);
set_reset_data( slcr__TZ_OCM_RAM1, val_slcr__TZ_OCM_RAM1);
set_reset_data( slcr__TZ_OCM_ROM, val_slcr__TZ_OCM_ROM);
set_reset_data( slcr__TZ_DDR_RAM, val_slcr__TZ_DDR_RAM);
set_reset_data( slcr__TZ_DMA_NS, val_slcr__TZ_DMA_NS);
set_reset_data( slcr__TZ_DMA_IRQ_NS, val_slcr__TZ_DMA_IRQ_NS);
set_reset_data( slcr__TZ_DMA_PERIPH_NS, val_slcr__TZ_DMA_PERIPH_NS);
set_reset_data( slcr__TZ_GEM, val_slcr__TZ_GEM);
set_reset_data( slcr__TZ_SDIO, val_slcr__TZ_SDIO);
set_reset_data( slcr__TZ_USB, val_slcr__TZ_USB);
set_reset_data( slcr__TZ_FPGA_M, val_slcr__TZ_FPGA_M);
set_reset_data( slcr__TZ_FPGA_AFI, val_slcr__TZ_FPGA_AFI);
set_reset_data( slcr__DBG_CTRL, val_slcr__DBG_CTRL);
set_reset_data( slcr__PSS_IDCODE, val_slcr__PSS_IDCODE);
set_reset_data( slcr__DDR_URGENT, val_slcr__DDR_URGENT);
set_reset_data( slcr__DDR_CAL_START, val_slcr__DDR_CAL_START);
set_reset_data( slcr__DDR_REF_START, val_slcr__DDR_REF_START);
set_reset_data( slcr__DDR_CMD_STA, val_slcr__DDR_CMD_STA);
set_reset_data( slcr__DDR_URGENT_SEL, val_slcr__DDR_URGENT_SEL);
set_reset_data( slcr__DDR_DFI_STATUS, val_slcr__DDR_DFI_STATUS);
set_reset_data( slcr__MIO_PIN_00, val_slcr__MIO_PIN_00);
set_reset_data( slcr__MIO_PIN_01, val_slcr__MIO_PIN_01);
set_reset_data( slcr__MIO_PIN_02, val_slcr__MIO_PIN_02);
set_reset_data( slcr__MIO_PIN_03, val_slcr__MIO_PIN_03);
set_reset_data( slcr__MIO_PIN_04, val_slcr__MIO_PIN_04);
set_reset_data( slcr__MIO_PIN_05, val_slcr__MIO_PIN_05);
set_reset_data( slcr__MIO_PIN_06, val_slcr__MIO_PIN_06);
set_reset_data( slcr__MIO_PIN_07, val_slcr__MIO_PIN_07);
set_reset_data( slcr__MIO_PIN_08, val_slcr__MIO_PIN_08);
set_reset_data( slcr__MIO_PIN_09, val_slcr__MIO_PIN_09);
set_reset_data( slcr__MIO_PIN_10, val_slcr__MIO_PIN_10);
set_reset_data( slcr__MIO_PIN_11, val_slcr__MIO_PIN_11);
set_reset_data( slcr__MIO_PIN_12, val_slcr__MIO_PIN_12);
set_reset_data( slcr__MIO_PIN_13, val_slcr__MIO_PIN_13);
set_reset_data( slcr__MIO_PIN_14, val_slcr__MIO_PIN_14);
set_reset_data( slcr__MIO_PIN_15, val_slcr__MIO_PIN_15);
set_reset_data( slcr__MIO_PIN_16, val_slcr__MIO_PIN_16);
set_reset_data( slcr__MIO_PIN_17, val_slcr__MIO_PIN_17);
set_reset_data( slcr__MIO_PIN_18, val_slcr__MIO_PIN_18);
set_reset_data( slcr__MIO_PIN_19, val_slcr__MIO_PIN_19);
set_reset_data( slcr__MIO_PIN_20, val_slcr__MIO_PIN_20);
set_reset_data( slcr__MIO_PIN_21, val_slcr__MIO_PIN_21);
set_reset_data( slcr__MIO_PIN_22, val_slcr__MIO_PIN_22);
set_reset_data( slcr__MIO_PIN_23, val_slcr__MIO_PIN_23);
set_reset_data( slcr__MIO_PIN_24, val_slcr__MIO_PIN_24);
set_reset_data( slcr__MIO_PIN_25, val_slcr__MIO_PIN_25);
set_reset_data( slcr__MIO_PIN_26, val_slcr__MIO_PIN_26);
set_reset_data( slcr__MIO_PIN_27, val_slcr__MIO_PIN_27);
set_reset_data( slcr__MIO_PIN_28, val_slcr__MIO_PIN_28);
set_reset_data( slcr__MIO_PIN_29, val_slcr__MIO_PIN_29);
set_reset_data( slcr__MIO_PIN_30, val_slcr__MIO_PIN_30);
set_reset_data( slcr__MIO_PIN_31, val_slcr__MIO_PIN_31);
set_reset_data( slcr__MIO_PIN_32, val_slcr__MIO_PIN_32);
set_reset_data( slcr__MIO_PIN_33, val_slcr__MIO_PIN_33);
set_reset_data( slcr__MIO_PIN_34, val_slcr__MIO_PIN_34);
set_reset_data( slcr__MIO_PIN_35, val_slcr__MIO_PIN_35);
set_reset_data( slcr__MIO_PIN_36, val_slcr__MIO_PIN_36);
set_reset_data( slcr__MIO_PIN_37, val_slcr__MIO_PIN_37);
set_reset_data( slcr__MIO_PIN_38, val_slcr__MIO_PIN_38);
set_reset_data( slcr__MIO_PIN_39, val_slcr__MIO_PIN_39);
set_reset_data( slcr__MIO_PIN_40, val_slcr__MIO_PIN_40);
set_reset_data( slcr__MIO_PIN_41, val_slcr__MIO_PIN_41);
set_reset_data( slcr__MIO_PIN_42, val_slcr__MIO_PIN_42);
set_reset_data( slcr__MIO_PIN_43, val_slcr__MIO_PIN_43);
set_reset_data( slcr__MIO_PIN_44, val_slcr__MIO_PIN_44);
set_reset_data( slcr__MIO_PIN_45, val_slcr__MIO_PIN_45);
set_reset_data( slcr__MIO_PIN_46, val_slcr__MIO_PIN_46);
set_reset_data( slcr__MIO_PIN_47, val_slcr__MIO_PIN_47);
set_reset_data( slcr__MIO_PIN_48, val_slcr__MIO_PIN_48);
set_reset_data( slcr__MIO_PIN_49, val_slcr__MIO_PIN_49);
set_reset_data( slcr__MIO_PIN_50, val_slcr__MIO_PIN_50);
set_reset_data( slcr__MIO_PIN_51, val_slcr__MIO_PIN_51);
set_reset_data( slcr__MIO_PIN_52, val_slcr__MIO_PIN_52);
set_reset_data( slcr__MIO_PIN_53, val_slcr__MIO_PIN_53);
set_reset_data( slcr__MIO_FMIO_GEM_SEL, val_slcr__MIO_FMIO_GEM_SEL);
set_reset_data( slcr__MIO_LOOPBACK, val_slcr__MIO_LOOPBACK);
set_reset_data( slcr__MIO_MST_TRI0, val_slcr__MIO_MST_TRI0);
set_reset_data( slcr__MIO_MST_TRI1, val_slcr__MIO_MST_TRI1);
set_reset_data( slcr__SD0_WP_CD_SEL, val_slcr__SD0_WP_CD_SEL);
set_reset_data( slcr__SD1_WP_CD_SEL, val_slcr__SD1_WP_CD_SEL);
set_reset_data( slcr__LVL_SHFTR_EN, val_slcr__LVL_SHFTR_EN);
set_reset_data( slcr__OCM_CFG, val_slcr__OCM_CFG);
set_reset_data( slcr__CPU0_RAM0, val_slcr__CPU0_RAM0);
set_reset_data( slcr__CPU0_RAM1, val_slcr__CPU0_RAM1);
set_reset_data( slcr__CPU0_RAM2, val_slcr__CPU0_RAM2);
set_reset_data( slcr__CPU1_RAM0, val_slcr__CPU1_RAM0);
set_reset_data( slcr__CPU1_RAM1, val_slcr__CPU1_RAM1);
set_reset_data( slcr__CPU1_RAM2, val_slcr__CPU1_RAM2);
set_reset_data( slcr__SCU_RAM, val_slcr__SCU_RAM);
set_reset_data( slcr__L2C_RAM, val_slcr__L2C_RAM);
set_reset_data( slcr__IOU_RAM_GEM01, val_slcr__IOU_RAM_GEM01);
set_reset_data( slcr__IOU_RAM_USB01, val_slcr__IOU_RAM_USB01);
set_reset_data( slcr__IOU_RAM_SDIO0, val_slcr__IOU_RAM_SDIO0);
set_reset_data( slcr__IOU_RAM_SDIO1, val_slcr__IOU_RAM_SDIO1);
set_reset_data( slcr__IOU_RAM_CAN0, val_slcr__IOU_RAM_CAN0);
set_reset_data( slcr__IOU_RAM_CAN1, val_slcr__IOU_RAM_CAN1);
set_reset_data( slcr__IOU_RAM_LQSPI, val_slcr__IOU_RAM_LQSPI);
set_reset_data( slcr__DMAC_RAM, val_slcr__DMAC_RAM);
set_reset_data( slcr__AFI0_RAM0, val_slcr__AFI0_RAM0);
set_reset_data( slcr__AFI0_RAM1, val_slcr__AFI0_RAM1);
set_reset_data( slcr__AFI0_RAM2, val_slcr__AFI0_RAM2);
set_reset_data( slcr__AFI1_RAM0, val_slcr__AFI1_RAM0);
set_reset_data( slcr__AFI1_RAM1, val_slcr__AFI1_RAM1);
set_reset_data( slcr__AFI1_RAM2, val_slcr__AFI1_RAM2);
set_reset_data( slcr__AFI2_RAM0, val_slcr__AFI2_RAM0);
set_reset_data( slcr__AFI2_RAM1, val_slcr__AFI2_RAM1);
set_reset_data( slcr__AFI2_RAM2, val_slcr__AFI2_RAM2);
set_reset_data( slcr__AFI3_RAM0, val_slcr__AFI3_RAM0);
set_reset_data( slcr__AFI3_RAM1, val_slcr__AFI3_RAM1);
set_reset_data( slcr__AFI3_RAM2, val_slcr__AFI3_RAM2);
set_reset_data( slcr__OCM_RAM, val_slcr__OCM_RAM);
set_reset_data( slcr__OCM_ROM0, val_slcr__OCM_ROM0);
set_reset_data( slcr__OCM_ROM1, val_slcr__OCM_ROM1);
set_reset_data( slcr__DEVCI_RAM, val_slcr__DEVCI_RAM);
set_reset_data( slcr__CSG_RAM, val_slcr__CSG_RAM);
set_reset_data( slcr__GPIOB_CTRL, val_slcr__GPIOB_CTRL);
set_reset_data( slcr__GPIOB_CFG_CMOS18, val_slcr__GPIOB_CFG_CMOS18);
set_reset_data( slcr__GPIOB_CFG_CMOS25, val_slcr__GPIOB_CFG_CMOS25);
set_reset_data( slcr__GPIOB_CFG_CMOS33, val_slcr__GPIOB_CFG_CMOS33);
set_reset_data( slcr__GPIOB_CFG_LVTTL, val_slcr__GPIOB_CFG_LVTTL);
set_reset_data( slcr__GPIOB_CFG_HSTL, val_slcr__GPIOB_CFG_HSTL);
set_reset_data( slcr__GPIOB_DRVR_BIAS_CTRL, val_slcr__GPIOB_DRVR_BIAS_CTRL);
set_reset_data( slcr__DDRIOB_ADDR0, val_slcr__DDRIOB_ADDR0);
set_reset_data( slcr__DDRIOB_ADDR1, val_slcr__DDRIOB_ADDR1);
set_reset_data( slcr__DDRIOB_DATA0, val_slcr__DDRIOB_DATA0);
set_reset_data( slcr__DDRIOB_DATA1, val_slcr__DDRIOB_DATA1);
set_reset_data( slcr__DDRIOB_DIFF0, val_slcr__DDRIOB_DIFF0);
set_reset_data( slcr__DDRIOB_DIFF1, val_slcr__DDRIOB_DIFF1);
set_reset_data( slcr__DDRIOB_CLOCK, val_slcr__DDRIOB_CLOCK);
set_reset_data( slcr__DDRIOB_DRIVE_SLEW_ADDR, val_slcr__DDRIOB_DRIVE_SLEW_ADDR);
set_reset_data( slcr__DDRIOB_DRIVE_SLEW_DATA, val_slcr__DDRIOB_DRIVE_SLEW_DATA);
set_reset_data( slcr__DDRIOB_DRIVE_SLEW_DIFF, val_slcr__DDRIOB_DRIVE_SLEW_DIFF);
set_reset_data( slcr__DDRIOB_DRIVE_SLEW_CLOCK, val_slcr__DDRIOB_DRIVE_SLEW_CLOCK);
set_reset_data( slcr__DDRIOB_DDR_CTRL, val_slcr__DDRIOB_DDR_CTRL);
set_reset_data( slcr__DDRIOB_DCI_CTRL, val_slcr__DDRIOB_DCI_CTRL);
set_reset_data( slcr__DDRIOB_DCI_STATUS, val_slcr__DDRIOB_DCI_STATUS);

// ************************************************************
//   Module smcc pl353
//   doc version: 1.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( smcc__memc_status, val_smcc__memc_status);
set_reset_data( smcc__memif_cfg, val_smcc__memif_cfg);
set_reset_data( smcc__memc_cfg_set, val_smcc__memc_cfg_set);
set_reset_data( smcc__memc_cfg_clr, val_smcc__memc_cfg_clr);
set_reset_data( smcc__direct_cmd, val_smcc__direct_cmd);
set_reset_data( smcc__set_cycles, val_smcc__set_cycles);
set_reset_data( smcc__set_opmode, val_smcc__set_opmode);
set_reset_data( smcc__refresh_period_0, val_smcc__refresh_period_0);
set_reset_data( smcc__refresh_period_1, val_smcc__refresh_period_1);
set_reset_data( smcc__sram_cycles0_0, val_smcc__sram_cycles0_0);
set_reset_data( smcc__opmode0_0, val_smcc__opmode0_0);
set_reset_data( smcc__sram_cycles0_1, val_smcc__sram_cycles0_1);
set_reset_data( smcc__opmode0_1, val_smcc__opmode0_1);
set_reset_data( smcc__nand_cycles1_0, val_smcc__nand_cycles1_0);
set_reset_data( smcc__opmode1_0, val_smcc__opmode1_0);
set_reset_data( smcc__user_status, val_smcc__user_status);
set_reset_data( smcc__user_config, val_smcc__user_config);
set_reset_data( smcc__ecc_status_0, val_smcc__ecc_status_0);
set_reset_data( smcc__ecc_memcfg_0, val_smcc__ecc_memcfg_0);
set_reset_data( smcc__ecc_memcommand1_0, val_smcc__ecc_memcommand1_0);
set_reset_data( smcc__ecc_memcommand2_0, val_smcc__ecc_memcommand2_0);
set_reset_data( smcc__ecc_addr0_0, val_smcc__ecc_addr0_0);
set_reset_data( smcc__ecc_addr1_0, val_smcc__ecc_addr1_0);
set_reset_data( smcc__ecc_value0_0, val_smcc__ecc_value0_0);
set_reset_data( smcc__ecc_value1_0, val_smcc__ecc_value1_0);
set_reset_data( smcc__ecc_value2_0, val_smcc__ecc_value2_0);
set_reset_data( smcc__ecc_value3_0, val_smcc__ecc_value3_0);
set_reset_data( smcc__ecc_status_1, val_smcc__ecc_status_1);
set_reset_data( smcc__ecc_memcfg_1, val_smcc__ecc_memcfg_1);
set_reset_data( smcc__ecc_memcommand1_1, val_smcc__ecc_memcommand1_1);
set_reset_data( smcc__ecc_memcommand2_1, val_smcc__ecc_memcommand2_1);
set_reset_data( smcc__ecc_addr0_1, val_smcc__ecc_addr0_1);
set_reset_data( smcc__ecc_addr1_1, val_smcc__ecc_addr1_1);
set_reset_data( smcc__ecc_value0_1, val_smcc__ecc_value0_1);
set_reset_data( smcc__ecc_value1_1, val_smcc__ecc_value1_1);
set_reset_data( smcc__ecc_value2_1, val_smcc__ecc_value2_1);
set_reset_data( smcc__ecc_value3_1, val_smcc__ecc_value3_1);
set_reset_data( smcc__integration_test, val_smcc__integration_test);
set_reset_data( smcc__periph_id_0, val_smcc__periph_id_0);
set_reset_data( smcc__periph_id_1, val_smcc__periph_id_1);
set_reset_data( smcc__periph_id_2, val_smcc__periph_id_2);
set_reset_data( smcc__periph_id_3, val_smcc__periph_id_3);
set_reset_data( smcc__pcell_id_0, val_smcc__pcell_id_0);
set_reset_data( smcc__pcell_id_1, val_smcc__pcell_id_1);
set_reset_data( smcc__pcell_id_2, val_smcc__pcell_id_2);
set_reset_data( smcc__pcell_id_3, val_smcc__pcell_id_3);

// ************************************************************
//   Module spi0 SPI
//   doc version: 1.2
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( spi0__Config_reg0, val_spi0__Config_reg0);
set_reset_data( spi0__Intr_status_reg0, val_spi0__Intr_status_reg0);
set_reset_data( spi0__Intrpt_en_reg0, val_spi0__Intrpt_en_reg0);
set_reset_data( spi0__Intrpt_dis_reg0, val_spi0__Intrpt_dis_reg0);
set_reset_data( spi0__Intrpt_mask_reg0, val_spi0__Intrpt_mask_reg0);
set_reset_data( spi0__En_reg0, val_spi0__En_reg0);
set_reset_data( spi0__Delay_reg0, val_spi0__Delay_reg0);
set_reset_data( spi0__Tx_data_reg0, val_spi0__Tx_data_reg0);
set_reset_data( spi0__Rx_data_reg0, val_spi0__Rx_data_reg0);
set_reset_data( spi0__Slave_Idle_count_reg0, val_spi0__Slave_Idle_count_reg0);
set_reset_data( spi0__TX_thres_reg0, val_spi0__TX_thres_reg0);
set_reset_data( spi0__RX_thres_reg0, val_spi0__RX_thres_reg0);
set_reset_data( spi0__Mod_id_reg0, val_spi0__Mod_id_reg0);

// ************************************************************
//   Module spi1 SPI
//   doc version: 1.2
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( spi1__Config_reg0, val_spi1__Config_reg0);
set_reset_data( spi1__Intr_status_reg0, val_spi1__Intr_status_reg0);
set_reset_data( spi1__Intrpt_en_reg0, val_spi1__Intrpt_en_reg0);
set_reset_data( spi1__Intrpt_dis_reg0, val_spi1__Intrpt_dis_reg0);
set_reset_data( spi1__Intrpt_mask_reg0, val_spi1__Intrpt_mask_reg0);
set_reset_data( spi1__En_reg0, val_spi1__En_reg0);
set_reset_data( spi1__Delay_reg0, val_spi1__Delay_reg0);
set_reset_data( spi1__Tx_data_reg0, val_spi1__Tx_data_reg0);
set_reset_data( spi1__Rx_data_reg0, val_spi1__Rx_data_reg0);
set_reset_data( spi1__Slave_Idle_count_reg0, val_spi1__Slave_Idle_count_reg0);
set_reset_data( spi1__TX_thres_reg0, val_spi1__TX_thres_reg0);
set_reset_data( spi1__RX_thres_reg0, val_spi1__RX_thres_reg0);
set_reset_data( spi1__Mod_id_reg0, val_spi1__Mod_id_reg0);

// ************************************************************
//   Module swdt swdt
//   doc version: 2.1
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( swdt__MODE, val_swdt__MODE);
set_reset_data( swdt__CONTROL, val_swdt__CONTROL);
set_reset_data( swdt__RESTART, val_swdt__RESTART);
set_reset_data( swdt__STATUS, val_swdt__STATUS);

// ************************************************************
//   Module ttc0 ttc
//   doc version: 2.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( ttc0__Clock_Control_1, val_ttc0__Clock_Control_1);
set_reset_data( ttc0__Clock_Control_2, val_ttc0__Clock_Control_2);
set_reset_data( ttc0__Clock_Control_3, val_ttc0__Clock_Control_3);
set_reset_data( ttc0__Counter_Control_1, val_ttc0__Counter_Control_1);
set_reset_data( ttc0__Counter_Control_2, val_ttc0__Counter_Control_2);
set_reset_data( ttc0__Counter_Control_3, val_ttc0__Counter_Control_3);
set_reset_data( ttc0__Counter_Value_1, val_ttc0__Counter_Value_1);
set_reset_data( ttc0__Counter_Value_2, val_ttc0__Counter_Value_2);
set_reset_data( ttc0__Counter_Value_3, val_ttc0__Counter_Value_3);
set_reset_data( ttc0__Interval_Counter_1, val_ttc0__Interval_Counter_1);
set_reset_data( ttc0__Interval_Counter_2, val_ttc0__Interval_Counter_2);
set_reset_data( ttc0__Interval_Counter_3, val_ttc0__Interval_Counter_3);
set_reset_data( ttc0__Match_1_Counter_1, val_ttc0__Match_1_Counter_1);
set_reset_data( ttc0__Match_1_Counter_2, val_ttc0__Match_1_Counter_2);
set_reset_data( ttc0__Match_1_Counter_3, val_ttc0__Match_1_Counter_3);
set_reset_data( ttc0__Match_2_Counter_1, val_ttc0__Match_2_Counter_1);
set_reset_data( ttc0__Match_2_Counter_2, val_ttc0__Match_2_Counter_2);
set_reset_data( ttc0__Match_2_Counter_3, val_ttc0__Match_2_Counter_3);
set_reset_data( ttc0__Match_3_Counter_1, val_ttc0__Match_3_Counter_1);
set_reset_data( ttc0__Match_3_Counter_2, val_ttc0__Match_3_Counter_2);
set_reset_data( ttc0__Match_3_Counter_3, val_ttc0__Match_3_Counter_3);
set_reset_data( ttc0__Interrupt_Register_1, val_ttc0__Interrupt_Register_1);
set_reset_data( ttc0__Interrupt_Register_2, val_ttc0__Interrupt_Register_2);
set_reset_data( ttc0__Interrupt_Register_3, val_ttc0__Interrupt_Register_3);
set_reset_data( ttc0__Interrupt_Enable_1, val_ttc0__Interrupt_Enable_1);
set_reset_data( ttc0__Interrupt_Enable_2, val_ttc0__Interrupt_Enable_2);
set_reset_data( ttc0__Interrupt_Enable_3, val_ttc0__Interrupt_Enable_3);
set_reset_data( ttc0__Event_Control_Timer_1, val_ttc0__Event_Control_Timer_1);
set_reset_data( ttc0__Event_Control_Timer_2, val_ttc0__Event_Control_Timer_2);
set_reset_data( ttc0__Event_Control_Timer_3, val_ttc0__Event_Control_Timer_3);
set_reset_data( ttc0__Event_Register_1, val_ttc0__Event_Register_1);
set_reset_data( ttc0__Event_Register_2, val_ttc0__Event_Register_2);
set_reset_data( ttc0__Event_Register_3, val_ttc0__Event_Register_3);

// ************************************************************
//   Module ttc1 ttc
//   doc version: 2.0
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( ttc1__Clock_Control_1, val_ttc1__Clock_Control_1);
set_reset_data( ttc1__Clock_Control_2, val_ttc1__Clock_Control_2);
set_reset_data( ttc1__Clock_Control_3, val_ttc1__Clock_Control_3);
set_reset_data( ttc1__Counter_Control_1, val_ttc1__Counter_Control_1);
set_reset_data( ttc1__Counter_Control_2, val_ttc1__Counter_Control_2);
set_reset_data( ttc1__Counter_Control_3, val_ttc1__Counter_Control_3);
set_reset_data( ttc1__Counter_Value_1, val_ttc1__Counter_Value_1);
set_reset_data( ttc1__Counter_Value_2, val_ttc1__Counter_Value_2);
set_reset_data( ttc1__Counter_Value_3, val_ttc1__Counter_Value_3);
set_reset_data( ttc1__Interval_Counter_1, val_ttc1__Interval_Counter_1);
set_reset_data( ttc1__Interval_Counter_2, val_ttc1__Interval_Counter_2);
set_reset_data( ttc1__Interval_Counter_3, val_ttc1__Interval_Counter_3);
set_reset_data( ttc1__Match_1_Counter_1, val_ttc1__Match_1_Counter_1);
set_reset_data( ttc1__Match_1_Counter_2, val_ttc1__Match_1_Counter_2);
set_reset_data( ttc1__Match_1_Counter_3, val_ttc1__Match_1_Counter_3);
set_reset_data( ttc1__Match_2_Counter_1, val_ttc1__Match_2_Counter_1);
set_reset_data( ttc1__Match_2_Counter_2, val_ttc1__Match_2_Counter_2);
set_reset_data( ttc1__Match_2_Counter_3, val_ttc1__Match_2_Counter_3);
set_reset_data( ttc1__Match_3_Counter_1, val_ttc1__Match_3_Counter_1);
set_reset_data( ttc1__Match_3_Counter_2, val_ttc1__Match_3_Counter_2);
set_reset_data( ttc1__Match_3_Counter_3, val_ttc1__Match_3_Counter_3);
set_reset_data( ttc1__Interrupt_Register_1, val_ttc1__Interrupt_Register_1);
set_reset_data( ttc1__Interrupt_Register_2, val_ttc1__Interrupt_Register_2);
set_reset_data( ttc1__Interrupt_Register_3, val_ttc1__Interrupt_Register_3);
set_reset_data( ttc1__Interrupt_Enable_1, val_ttc1__Interrupt_Enable_1);
set_reset_data( ttc1__Interrupt_Enable_2, val_ttc1__Interrupt_Enable_2);
set_reset_data( ttc1__Interrupt_Enable_3, val_ttc1__Interrupt_Enable_3);
set_reset_data( ttc1__Event_Control_Timer_1, val_ttc1__Event_Control_Timer_1);
set_reset_data( ttc1__Event_Control_Timer_2, val_ttc1__Event_Control_Timer_2);
set_reset_data( ttc1__Event_Control_Timer_3, val_ttc1__Event_Control_Timer_3);
set_reset_data( ttc1__Event_Register_1, val_ttc1__Event_Register_1);
set_reset_data( ttc1__Event_Register_2, val_ttc1__Event_Register_2);
set_reset_data( ttc1__Event_Register_3, val_ttc1__Event_Register_3);

// ************************************************************
//   Module uart0 UART
//   doc version: 1.2
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( uart0__Control_reg0, val_uart0__Control_reg0);
set_reset_data( uart0__mode_reg0, val_uart0__mode_reg0);
set_reset_data( uart0__Intrpt_en_reg0, val_uart0__Intrpt_en_reg0);
set_reset_data( uart0__Intrpt_dis_reg0, val_uart0__Intrpt_dis_reg0);
set_reset_data( uart0__Intrpt_mask_reg0, val_uart0__Intrpt_mask_reg0);
set_reset_data( uart0__Chnl_int_sts_reg0, val_uart0__Chnl_int_sts_reg0);
set_reset_data( uart0__Baud_rate_gen_reg0, val_uart0__Baud_rate_gen_reg0);
set_reset_data( uart0__Rcvr_timeout_reg0, val_uart0__Rcvr_timeout_reg0);
set_reset_data( uart0__Rcvr_FIFO_trigger_level0, val_uart0__Rcvr_FIFO_trigger_level0);
set_reset_data( uart0__Modem_ctrl_reg0, val_uart0__Modem_ctrl_reg0);
set_reset_data( uart0__Modem_sts_reg0, val_uart0__Modem_sts_reg0);
set_reset_data( uart0__Channel_sts_reg0, val_uart0__Channel_sts_reg0);
set_reset_data( uart0__TX_RX_FIFO0, val_uart0__TX_RX_FIFO0);
set_reset_data( uart0__Baud_rate_divider_reg0, val_uart0__Baud_rate_divider_reg0);
set_reset_data( uart0__Flow_delay_reg0, val_uart0__Flow_delay_reg0);
set_reset_data( uart0__IR_min_rcv_pulse_wdth0, val_uart0__IR_min_rcv_pulse_wdth0);
set_reset_data( uart0__IR_transmitted_pulse_wdth0, val_uart0__IR_transmitted_pulse_wdth0);
set_reset_data( uart0__Tx_FIFO_trigger_level0, val_uart0__Tx_FIFO_trigger_level0);

// ************************************************************
//   Module uart1 UART
//   doc version: 1.2
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( uart1__Control_reg0, val_uart1__Control_reg0);
set_reset_data( uart1__mode_reg0, val_uart1__mode_reg0);
set_reset_data( uart1__Intrpt_en_reg0, val_uart1__Intrpt_en_reg0);
set_reset_data( uart1__Intrpt_dis_reg0, val_uart1__Intrpt_dis_reg0);
set_reset_data( uart1__Intrpt_mask_reg0, val_uart1__Intrpt_mask_reg0);
set_reset_data( uart1__Chnl_int_sts_reg0, val_uart1__Chnl_int_sts_reg0);
set_reset_data( uart1__Baud_rate_gen_reg0, val_uart1__Baud_rate_gen_reg0);
set_reset_data( uart1__Rcvr_timeout_reg0, val_uart1__Rcvr_timeout_reg0);
set_reset_data( uart1__Rcvr_FIFO_trigger_level0, val_uart1__Rcvr_FIFO_trigger_level0);
set_reset_data( uart1__Modem_ctrl_reg0, val_uart1__Modem_ctrl_reg0);
set_reset_data( uart1__Modem_sts_reg0, val_uart1__Modem_sts_reg0);
set_reset_data( uart1__Channel_sts_reg0, val_uart1__Channel_sts_reg0);
set_reset_data( uart1__TX_RX_FIFO0, val_uart1__TX_RX_FIFO0);
set_reset_data( uart1__Baud_rate_divider_reg0, val_uart1__Baud_rate_divider_reg0);
set_reset_data( uart1__Flow_delay_reg0, val_uart1__Flow_delay_reg0);
set_reset_data( uart1__IR_min_rcv_pulse_wdth0, val_uart1__IR_min_rcv_pulse_wdth0);
set_reset_data( uart1__IR_transmitted_pulse_wdth0, val_uart1__IR_transmitted_pulse_wdth0);
set_reset_data( uart1__Tx_FIFO_trigger_level0, val_uart1__Tx_FIFO_trigger_level0);

// ************************************************************
//   Module usb0 usb
//   doc version: 1.3
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( usb0__ID, val_usb0__ID);
set_reset_data( usb0__HWGENERAL, val_usb0__HWGENERAL);
set_reset_data( usb0__HWHOST, val_usb0__HWHOST);
set_reset_data( usb0__HWDEVICE, val_usb0__HWDEVICE);
set_reset_data( usb0__HWTXBUF, val_usb0__HWTXBUF);
set_reset_data( usb0__HWRXBUF, val_usb0__HWRXBUF);
set_reset_data( usb0__GPTIMER0LD, val_usb0__GPTIMER0LD);
set_reset_data( usb0__GPTIMER0CTRL, val_usb0__GPTIMER0CTRL);
set_reset_data( usb0__GPTIMER1LD, val_usb0__GPTIMER1LD);
set_reset_data( usb0__GPTIMER1CTRL, val_usb0__GPTIMER1CTRL);
set_reset_data( usb0__SBUSCFG, val_usb0__SBUSCFG);
set_reset_data( usb0__CAPLENGTH_HCIVERSION, val_usb0__CAPLENGTH_HCIVERSION);
set_reset_data( usb0__HCSPARAMS, val_usb0__HCSPARAMS);
set_reset_data( usb0__HCCPARAMS, val_usb0__HCCPARAMS);
set_reset_data( usb0__DCIVERSION, val_usb0__DCIVERSION);
set_reset_data( usb0__DCCPARAMS, val_usb0__DCCPARAMS);
set_reset_data( usb0__USBCMD, val_usb0__USBCMD);
set_reset_data( usb0__USBSTS, val_usb0__USBSTS);
set_reset_data( usb0__USBINTR, val_usb0__USBINTR);
set_reset_data( usb0__FRINDEX, val_usb0__FRINDEX);
set_reset_data( usb0__PERIODICLISTBASE_DEVICEADDR, val_usb0__PERIODICLISTBASE_DEVICEADDR);
set_reset_data( usb0__ASYNCLISTADDR_ENDPOINTLISTADDR, val_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR);
set_reset_data( usb0__TTCTRL, val_usb0__TTCTRL);
set_reset_data( usb0__BURSTSIZE, val_usb0__BURSTSIZE);
set_reset_data( usb0__TXFILLTUNING, val_usb0__TXFILLTUNING);
set_reset_data( usb0__TXTTFILLTUNING, val_usb0__TXTTFILLTUNING);
set_reset_data( usb0__IC_USB, val_usb0__IC_USB);
set_reset_data( usb0__ULPI_VIEWPORT, val_usb0__ULPI_VIEWPORT);
set_reset_data( usb0__ENDPTNAK, val_usb0__ENDPTNAK);
set_reset_data( usb0__ENDPTNAKEN, val_usb0__ENDPTNAKEN);
set_reset_data( usb0__CONFIGFLAG, val_usb0__CONFIGFLAG);
set_reset_data( usb0__PORTSC1, val_usb0__PORTSC1);
set_reset_data( usb0__OTGSC, val_usb0__OTGSC);
set_reset_data( usb0__USBMODE, val_usb0__USBMODE);
set_reset_data( usb0__ENDPTSETUPSTAT, val_usb0__ENDPTSETUPSTAT);
set_reset_data( usb0__ENDPTPRIME, val_usb0__ENDPTPRIME);
set_reset_data( usb0__ENDPTFLUSH, val_usb0__ENDPTFLUSH);
set_reset_data( usb0__ENDPTSTAT, val_usb0__ENDPTSTAT);
set_reset_data( usb0__ENDPTCOMPLETE, val_usb0__ENDPTCOMPLETE);
set_reset_data( usb0__ENDPTCTRL0, val_usb0__ENDPTCTRL0);
set_reset_data( usb0__ENDPTCTRL1, val_usb0__ENDPTCTRL1);
set_reset_data( usb0__ENDPTCTRL2, val_usb0__ENDPTCTRL2);
set_reset_data( usb0__ENDPTCTRL3, val_usb0__ENDPTCTRL3);
set_reset_data( usb0__ENDPTCTRL4, val_usb0__ENDPTCTRL4);
set_reset_data( usb0__ENDPTCTRL5, val_usb0__ENDPTCTRL5);
set_reset_data( usb0__ENDPTCTRL6, val_usb0__ENDPTCTRL6);
set_reset_data( usb0__ENDPTCTRL7, val_usb0__ENDPTCTRL7);
set_reset_data( usb0__ENDPTCTRL8, val_usb0__ENDPTCTRL8);
set_reset_data( usb0__ENDPTCTRL9, val_usb0__ENDPTCTRL9);
set_reset_data( usb0__ENDPTCTRL10, val_usb0__ENDPTCTRL10);
set_reset_data( usb0__ENDPTCTRL11, val_usb0__ENDPTCTRL11);
set_reset_data( usb0__ENDPTCTRL12, val_usb0__ENDPTCTRL12);

// ************************************************************
//   Module usb1 usb
//   doc version: 1.3
// ************************************************************

// ADDRESS  DEVFALUE   MASK       NAME
set_reset_data( usb1__ID, val_usb1__ID);
set_reset_data( usb1__HWGENERAL, val_usb1__HWGENERAL);
set_reset_data( usb1__HWHOST, val_usb1__HWHOST);
set_reset_data( usb1__HWDEVICE, val_usb1__HWDEVICE);
set_reset_data( usb1__HWTXBUF, val_usb1__HWTXBUF);
set_reset_data( usb1__HWRXBUF, val_usb1__HWRXBUF);
set_reset_data( usb1__GPTIMER0LD, val_usb1__GPTIMER0LD);
set_reset_data( usb1__GPTIMER0CTRL, val_usb1__GPTIMER0CTRL);
set_reset_data( usb1__GPTIMER1LD, val_usb1__GPTIMER1LD);
set_reset_data( usb1__GPTIMER1CTRL, val_usb1__GPTIMER1CTRL);
set_reset_data( usb1__SBUSCFG, val_usb1__SBUSCFG);
set_reset_data( usb1__CAPLENGTH_HCIVERSION, val_usb1__CAPLENGTH_HCIVERSION);
set_reset_data( usb1__HCSPARAMS, val_usb1__HCSPARAMS);
set_reset_data( usb1__HCCPARAMS, val_usb1__HCCPARAMS);
set_reset_data( usb1__DCIVERSION, val_usb1__DCIVERSION);
set_reset_data( usb1__DCCPARAMS, val_usb1__DCCPARAMS);
set_reset_data( usb1__USBCMD, val_usb1__USBCMD);
set_reset_data( usb1__USBSTS, val_usb1__USBSTS);
set_reset_data( usb1__USBINTR, val_usb1__USBINTR);
set_reset_data( usb1__FRINDEX, val_usb1__FRINDEX);
set_reset_data( usb1__PERIODICLISTBASE_DEVICEADDR, val_usb1__PERIODICLISTBASE_DEVICEADDR);
set_reset_data( usb1__ASYNCLISTADDR_ENDPOINTLISTADDR, val_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR);
set_reset_data( usb1__TTCTRL, val_usb1__TTCTRL);
set_reset_data( usb1__BURSTSIZE, val_usb1__BURSTSIZE);
set_reset_data( usb1__TXFILLTUNING, val_usb1__TXFILLTUNING);
set_reset_data( usb1__TXTTFILLTUNING, val_usb1__TXTTFILLTUNING);
set_reset_data( usb1__IC_USB, val_usb1__IC_USB);
set_reset_data( usb1__ULPI_VIEWPORT, val_usb1__ULPI_VIEWPORT);
set_reset_data( usb1__ENDPTNAK, val_usb1__ENDPTNAK);
set_reset_data( usb1__ENDPTNAKEN, val_usb1__ENDPTNAKEN);
set_reset_data( usb1__CONFIGFLAG, val_usb1__CONFIGFLAG);
set_reset_data( usb1__PORTSC1, val_usb1__PORTSC1);
set_reset_data( usb1__OTGSC, val_usb1__OTGSC);
set_reset_data( usb1__USBMODE, val_usb1__USBMODE);
set_reset_data( usb1__ENDPTSETUPSTAT, val_usb1__ENDPTSETUPSTAT);
set_reset_data( usb1__ENDPTPRIME, val_usb1__ENDPTPRIME);
set_reset_data( usb1__ENDPTFLUSH, val_usb1__ENDPTFLUSH);
set_reset_data( usb1__ENDPTSTAT, val_usb1__ENDPTSTAT);
set_reset_data( usb1__ENDPTCOMPLETE, val_usb1__ENDPTCOMPLETE);
set_reset_data( usb1__ENDPTCTRL0, val_usb1__ENDPTCTRL0);
set_reset_data( usb1__ENDPTCTRL1, val_usb1__ENDPTCTRL1);
set_reset_data( usb1__ENDPTCTRL2, val_usb1__ENDPTCTRL2);
set_reset_data( usb1__ENDPTCTRL3, val_usb1__ENDPTCTRL3);
set_reset_data( usb1__ENDPTCTRL4, val_usb1__ENDPTCTRL4);
set_reset_data( usb1__ENDPTCTRL5, val_usb1__ENDPTCTRL5);
set_reset_data( usb1__ENDPTCTRL6, val_usb1__ENDPTCTRL6);
set_reset_data( usb1__ENDPTCTRL7, val_usb1__ENDPTCTRL7);
set_reset_data( usb1__ENDPTCTRL8, val_usb1__ENDPTCTRL8);
set_reset_data( usb1__ENDPTCTRL9, val_usb1__ENDPTCTRL9);
set_reset_data( usb1__ENDPTCTRL10, val_usb1__ENDPTCTRL10);
set_reset_data( usb1__ENDPTCTRL11, val_usb1__ENDPTCTRL11);
set_reset_data( usb1__ENDPTCTRL12, val_usb1__ENDPTCTRL12);
