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// IP VLNV: analog.com:user:util_tdd_sync:1.0
// IP Revision: 1

`timescale 1ns/1ps

(* IP_DEFINITION_SOURCE = "package_project" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_util_ad9361_tdd_sync_0 (
  clk,
  rstn,
  sync_mode,
  sync_in,
  sync_out
);

(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rstn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_sys_ps7_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME rstn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 rstn RST" *)
input wire rstn;
input wire sync_mode;
input wire sync_in;
output wire sync_out;

  util_tdd_sync #(
    .TDD_SYNC_PERIOD(10000000)
  ) inst (
    .clk(clk),
    .rstn(rstn),
    .sync_mode(sync_mode),
    .sync_in(sync_in),
    .sync_out(sync_out)
  );
endmodule
