# 
# Synthesis run script generated by Vivado
# 

set TIME_start [clock seconds] 
proc create_report { reportName command } {
  set status "."
  append status $reportName ".fail"
  if { [file exists $status] } {
    eval file delete [glob $status]
  }
  send_msg_id runtcl-4 info "Executing : $command"
  set retval [eval catch { $command } msg]
  if { $retval != 0 } {
    set fp [open $status w]
    close $fp
    send_msg_id runtcl-5 warning "$msg"
  }
}
set_param simulator.modelsimInstallPath C:/modeltech64_2019.2/win64
set_msg_config  -id {Vivado 12-1790}  -string {{Evaluation} {features} {should} {NOT} {be} {used} {in} {production} {systems.}}  -new_severity {WARNING} 
set_msg_config  -id {Place 30-73}  -string {{axi_spi}}  -new_severity {WARNING} 
set_msg_config  -string {{PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY}}  -new_severity {WARNING} 
set_msg_config  -id {BD 41-1343}  -new_severity {WARNING} 
set_msg_config  -id {BD 41-1306}  -new_severity {WARNING} 
set_msg_config  -id {BD 41-1276}  -severity {CRITICAL WARNING}  -new_severity {ERROR} 
set_msg_config  -id {IP_Flow 19-3656}  -new_severity {INFO} 
set_msg_config  -id {IP_Flow 19-4623}  -new_severity {INFO} 
set_msg_config  -id {IP_Flow 19-459}  -new_severity {INFO} 
set_msg_config  -id {Synth 8-3331}  -new_severity {INFO} 
set_msg_config  -id {Designutils 20-3303}  -string {{HDPYFinalizeIO}}  -new_severity {INFO} 
create_project -in_memory -part xc7z045ffg900-2

set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir E:/Projects/sdr_b1_v11/sdr_b1.cache/wt [current_project]
set_property parent.project_path E:/Projects/sdr_b1_v11/sdr_b1.xpr [current_project]
set_property XPM_LIBRARIES {XPM_CDC XPM_FIFO XPM_MEMORY} [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_repo_paths {
  e:/Temp/prj/hdl-hdl_2019_r2/library
  e:/Temp/prj/ghdl/library
} [current_project]
update_ip_catalog
set_property ip_output_repo e:/Projects/sdr_b1_v11/sdr_b1.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
read_verilog -library xil_defaultlib {
  E:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/imports/hdl-hdl_2019_r2/library/common/ad_iobuf.v
  E:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/imports/hdl/system_wrapper.v
  E:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/imports/hdl-hdl_2019_r2/projects/adrv9361z7035/ccbob_lvds/system_top.v
}
add_files E:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/system.bd
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_sys_ps7_0/system_sys_ps7_0.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_iic_main_0/system_axi_iic_main_0_board.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_iic_main_0/system_axi_iic_main_0_ooc.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/system_sys_rstgen_0_board.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/system_sys_rstgen_0.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/system_axi_ad9361_0_pps_constr.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_cntrl_constr.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/xilinx/common/up_xfer_status_constr.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/xilinx/common/up_clock_mon_constr.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/axi_ad9361_constr.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_util_ad9361_tdd_sync_0/util_tdd_sync_constr.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_0/system_util_ad9361_divclk_0_ooc.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_0/util_clkdiv_constr.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_reset_0/system_util_ad9361_divclk_reset_0_board.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_util_ad9361_divclk_reset_0/system_util_ad9361_divclk_reset_0.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_ad9361_adc_dma_0/system_axi_ad9361_adc_dma_0_constr.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_fifo_0/util_rfifo_constr.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_dma_0/system_axi_ad9361_dac_dma_0_constr.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/ooc.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_1/bd_31bd_psr_aclk_0_board.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_1/bd_31bd_psr_aclk_0.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_5/bd_31bd_s00a2s_0_ooc.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_6/bd_31bd_sawn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_7/bd_31bd_swn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_8/bd_31bd_sbn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_hp1_interconnect_0/bd_0/ip/ip_9/bd_31bd_m00s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/ooc.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_1/bd_c0fd_psr_aclk_0_board.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_1/bd_c0fd_psr_aclk_0.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_5/bd_c0fd_s00a2s_0_ooc.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_6/bd_c0fd_sarn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_7/bd_c0fd_srn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_hp2_interconnect_0/bd_0/ip/ip_8/bd_c0fd_m00s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_axi_gpreg_0/system_axi_gpreg_0_constr.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/xilinx/common/ad_rst_constr.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_xbar_0/system_xbar_0_ooc.xdc]
set_property used_in_implementation false [get_files -all e:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/ip/system_auto_pc_0/system_auto_pc_0_ooc.xdc]
set_property used_in_implementation false [get_files -all E:/Projects/sdr_b1_v11/sdr_b1.srcs/sources_1/bd/system/system_ooc.xdc]

# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
  set_property used_in_implementation false $dcp
}
read_xdc E:/Projects/sdr_b1_v11/sdr_b1.srcs/constrs_1/new/sdr_b1.xdc
set_property used_in_implementation false [get_files E:/Projects/sdr_b1_v11/sdr_b1.srcs/constrs_1/new/sdr_b1.xdc]

read_xdc dont_touch.xdc
set_property used_in_implementation false [get_files dont_touch.xdc]
set_param ips.enableIPCacheLiteLoad 1
close [open __synthesis_is_running__ w]

synth_design -top system_top -part xc7z045ffg900-2


# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef system_top.dcp
create_report "synth_1_synth_report_utilization_0" "report_utilization -file system_top_utilization_synth.rpt -pb system_top_utilization_synth.pb"
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]
