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// IP VLNV: analog.com:user:util_wfifo:1.0
// IP Revision: 1

`timescale 1ns/1ps

(* IP_DEFINITION_SOURCE = "package_project" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_util_ad9361_adc_fifo_0 (
  din_rst,
  din_clk,
  din_enable_0,
  din_valid_0,
  din_data_0,
  din_enable_1,
  din_valid_1,
  din_data_1,
  din_enable_2,
  din_valid_2,
  din_data_2,
  din_enable_3,
  din_valid_3,
  din_data_3,
  din_ovf,
  dout_rstn,
  dout_clk,
  dout_enable_0,
  dout_valid_0,
  dout_data_0,
  dout_enable_1,
  dout_valid_1,
  dout_data_1,
  dout_enable_2,
  dout_valid_2,
  dout_data_2,
  dout_enable_3,
  dout_valid_3,
  dout_data_3,
  dout_ovf
);

(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME din_rst, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 din_rst RST" *)
input wire din_rst;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME din_clk, ASSOCIATED_RESET din_rst, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_axi_ad9361_0_l_clk, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 din_clk CLK" *)
input wire din_clk;
input wire din_enable_0;
input wire din_valid_0;
input wire [15 : 0] din_data_0;
input wire din_enable_1;
input wire din_valid_1;
input wire [15 : 0] din_data_1;
input wire din_enable_2;
input wire din_valid_2;
input wire [15 : 0] din_data_2;
input wire din_enable_3;
input wire din_valid_3;
input wire [15 : 0] din_data_3;
output wire din_ovf;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME dout_rstn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 dout_rstn RST" *)
input wire dout_rstn;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME dout_clk, ASSOCIATED_RESET dout_rstn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_util_ad9361_divclk_0_clk_out, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 dout_clk CLK" *)
input wire dout_clk;
output wire dout_enable_0;
output wire dout_valid_0;
output wire [15 : 0] dout_data_0;
output wire dout_enable_1;
output wire dout_valid_1;
output wire [15 : 0] dout_data_1;
output wire dout_enable_2;
output wire dout_valid_2;
output wire [15 : 0] dout_data_2;
output wire dout_enable_3;
output wire dout_valid_3;
output wire [15 : 0] dout_data_3;
input wire dout_ovf;

  util_wfifo #(
    .NUM_OF_CHANNELS(4),
    .DIN_DATA_WIDTH(16),
    .DOUT_DATA_WIDTH(16),
    .DIN_ADDRESS_WIDTH(4)
  ) inst (
    .din_rst(din_rst),
    .din_clk(din_clk),
    .din_enable_0(din_enable_0),
    .din_valid_0(din_valid_0),
    .din_data_0(din_data_0),
    .din_enable_1(din_enable_1),
    .din_valid_1(din_valid_1),
    .din_data_1(din_data_1),
    .din_enable_2(din_enable_2),
    .din_valid_2(din_valid_2),
    .din_data_2(din_data_2),
    .din_enable_3(din_enable_3),
    .din_valid_3(din_valid_3),
    .din_data_3(din_data_3),
    .din_enable_4(1'B0),
    .din_valid_4(1'B0),
    .din_data_4(16'B0),
    .din_enable_5(1'B0),
    .din_valid_5(1'B0),
    .din_data_5(16'B0),
    .din_enable_6(1'B0),
    .din_valid_6(1'B0),
    .din_data_6(16'B0),
    .din_enable_7(1'B0),
    .din_valid_7(1'B0),
    .din_data_7(16'B0),
    .din_ovf(din_ovf),
    .dout_rstn(dout_rstn),
    .dout_clk(dout_clk),
    .dout_enable_0(dout_enable_0),
    .dout_valid_0(dout_valid_0),
    .dout_data_0(dout_data_0),
    .dout_enable_1(dout_enable_1),
    .dout_valid_1(dout_valid_1),
    .dout_data_1(dout_data_1),
    .dout_enable_2(dout_enable_2),
    .dout_valid_2(dout_valid_2),
    .dout_data_2(dout_data_2),
    .dout_enable_3(dout_enable_3),
    .dout_valid_3(dout_valid_3),
    .dout_data_3(dout_data_3),
    .dout_enable_4(),
    .dout_valid_4(),
    .dout_data_4(),
    .dout_enable_5(),
    .dout_valid_5(),
    .dout_data_5(),
    .dout_enable_6(),
    .dout_valid_6(),
    .dout_data_6(),
    .dout_enable_7(),
    .dout_valid_7(),
    .dout_data_7(),
    .dout_ovf(dout_ovf)
  );
endmodule
