### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
beta | FALSE | build_version | 2552052
date_generated | Wed Jun 26 13:50:30 2024 | os_platform | WIN64
product_version | Vivado v2019.1 (64-bit) | project_id | 7ca949f1b9fd4096a38acd7194348d9b
project_iteration | 10 | random_id | 46f104e138ed53448d438104eb11616b
registration_id | 46f104e138ed53448d438104eb11616b | route_design | TRUE
target_device | xc7z045 | target_family | zynq
target_package | ffg900 | target_speed | -2
tool_flow | Vivado

user_environment
cpu_name | 11th Gen Intel(R) Core(TM) i7-11700K @ 3.60GHz | cpu_speed | 3600 MHz
os_name | Windows Server 2016 or Windows 10 | os_release | major release (build 9200)
system_ram | 34.000 GB | total_processors | 1

vivado_usage

gui_handlers
abstractsearchablepanel_show_search=1 | addsrcwizard_specify_or_create_constraint_files=1 | basedialog_apply=1 | basedialog_cancel=21
basedialog_no=2 | basedialog_ok=31 | basedialog_yes=6 | basereporttab_rerun=1
cmdmsgdialog_ok=1 | constraintschooserpanel_add_files=1 | constraintschooserpanel_create_file=1 | createconstraintsfilepanel_file_name=1
ddrconfigtreetablepanel_ddr_config_tree_table=60 | filesetpanel_file_set_panel_tree=157 | floatingtopdialog_ignore_and_continue_with_invalid_top=1 | flownavigatortreepanel_flow_navigator_tree=14
fpgachooser_family=1 | fpgachooser_fpga_table=1 | fpgachooser_package=2 | fpgachooser_speed=1
gensettingtreetablepanel_gen_setting_tree_table=40 | gettingstartedview_clear_list=1 | gettingstartedview_open_project=5 | hinputhandler_toggle_line_comments=4
ipstatussectionpanel_upgrade_selected=1 | mainmenumgr_checkpoint=9 | mainmenumgr_export=11 | mainmenumgr_file=20
mainmenumgr_ip=9 | mainmenumgr_open_recent_project=1 | mainmenumgr_project=10 | mainmenumgr_text_editor=9
mioconfigtreetablepanel_mio_config_tree_table=26 | miotablepagepanel_mio_table=36 | miotablepagepanel_mio_table_parameter=2 | msgtreepanel_message_view_tree=1
msgview_information_messages=2 | msgview_warning_messages=2 | newexporthardwaredialog_include_bitstream=6 | pacommandnames_export_bitstream_files=1
pacommandnames_export_hardware=6 | pacommandnames_generate_composite_file=1 | pacommandnames_launch_hardware=1 | pacommandnames_regenerate_layout=8
pacommandnames_save_project_as=1 | pacommandnames_save_rsb_design=1 | pacommandnames_validate_rsb_design=6 | pacommandnames_zoom_fit=2
paviews_code=4 | paviews_project_summary=21 | progressdialog_cancel=1 | projectnamechooser_choose_project_location=1
projectnamechooser_project_name=1 | rdicommands_delete=1 | rdicommands_save_file=2 | removesourcesdialog_also_delete=1
saveprojectutils_save=3 | settingsprojectgeneralpage_choose_device_for_your_project=1 | simpleoutputproductdialog_generate_output_products_immediately=2 | syntheticagettingstartedview_recent_projects=23
systemtab_report_ip_status=2 | systemtreeview_system_tree=2 | tclconsoleview_tcl_console_code_editor=1 | touchpointsurveydialog_no=2
zynqpanel_summary_report=1

java_command_handlers
addsources=1 | customizersbblock=27 | editdelete=8 | exportbitfile=1
managecompositetargets=1 | newexporthardware=6 | newlaunchhardware=1 | openproject=5
regeneratersblayout=8 | reportipstatus=2 | runbitgen=11 | saveprojectas=1
saversbdesign=2 | showview=1 | toolssettings=1 | upgradeip=1
validatersbdesign=6 | viewtaskprojectmanager=1 | zoomfit=2

other_data
batchmode=1 | guimode=29

project_data
constraintsetcount=1 | core_container=false | currentimplrun=impl_1 | currentsynthesisrun=synth_1
default_library=xil_defaultlib | designmode=RTL | export_simulation_activehdl=2 | export_simulation_ies=2
export_simulation_modelsim=2 | export_simulation_questa=2 | export_simulation_riviera=2 | export_simulation_vcs=2
export_simulation_xsim=2 | implstrategy=Vivado Implementation Defaults | launch_simulation_activehdl=0 | launch_simulation_ies=0
launch_simulation_modelsim=0 | launch_simulation_questa=0 | launch_simulation_riviera=0 | launch_simulation_vcs=0
launch_simulation_xsim=0 | simulator_language=Mixed | srcsetcount=4 | synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog | target_simulator=XSim | totalimplruns=1 | totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bibuf=130 | bufg=5 | bufgctrl=1 | bufr=2
carry4=1641 | dsp48e1=28 | fdce=4240 | fdpe=166
fdre=16128 | fdse=310 | gnd=471 | ibuf=25
ibufds=8 | iddr=7 | idelayctrl=1 | idelaye2=7
lut1=2097 | lut2=1916 | lut3=6062 | lut4=1164
lut5=1244 | lut6=2978 | muxf7=27 | muxf8=4
obuf=11 | obufds=8 | obuft=18 | oddr=10
odelaye2=10 | ps7=1 | ramb36e1=4 | ramd32=612
rams32=200 | srl16e=715 | srlc32e=47 | vcc=496
pre_unisim_transformation
bibuf=130 | bufg=5 | bufgctrl=1 | bufr=2
carry4=1641 | dsp48e1=28 | fdce=4240 | fdpe=166
fdre=16128 | fdse=310 | gnd=471 | ibuf=7
ibufds=8 | iddr=7 | idelayctrl=1 | idelaye2=7
iobuf=18 | lut1=2097 | lut2=1916 | lut3=6062
lut4=1164 | lut5=1244 | lut6=2978 | muxf7=27
muxf8=4 | obuf=11 | obufds=8 | oddr=10
odelaye2=10 | ps7=1 | ram32m=100 | ram32x1d=6
ramb36e1=4 | srl16e=715 | srlc32e=47 | vcc=496

power_opt_design
command_line_options_spo
-cell_types=default::all | -clocks=default::[not_specified] | -exclude_cells=default::[not_specified] | -include_cells=default::[not_specified]
usage
bram_ports_augmented=2 | bram_ports_newly_gated=7 | bram_ports_total=8 | flow_state=default
slice_registers_augmented=0 | slice_registers_newly_gated=0 | slice_registers_total=19887 | srls_augmented=0
srls_newly_gated=0 | srls_total=735

ip_statistics
IP_Integrator/1
bdsource=SBD | core_container=NA | iptotal=1 | maxhierdepth=1
numblks=15 | numhdlrefblks=0 | numhierblks=4 | numhlsblks=0
numnonxlnxblks=0 | numpkgbdblks=0 | numreposblks=11 | numsysgenblks=0
synth_mode=Global | x_iplanguage=VERILOG | x_iplibrary=BlockDiagram | x_ipname=bd_31bd
x_ipvendor=xilinx.com | x_ipversion=1.00.a
IP_Integrator/2
bdsource=SBD | core_container=NA | iptotal=1 | maxhierdepth=1
numblks=14 | numhdlrefblks=0 | numhierblks=4 | numhlsblks=0
numnonxlnxblks=0 | numpkgbdblks=0 | numreposblks=10 | numsysgenblks=0
synth_mode=Global | x_iplanguage=VERILOG | x_iplibrary=BlockDiagram | x_ipname=bd_c0fd
x_ipvendor=xilinx.com | x_ipversion=1.00.a
IP_Integrator/3
bdsource=USER | core_container=NA | iptotal=1 | maxhierdepth=0
numblks=33 | numhdlrefblks=0 | numhierblks=8 | numhlsblks=0
numnonxlnxblks=12 | numpkgbdblks=0 | numreposblks=25 | numsysgenblks=0
synth_mode=Global | x_iplanguage=VERILOG | x_iplibrary=BlockDiagram | x_ipname=system
x_ipvendor=xilinx.com | x_ipversion=1.00.a
axi_crossbar_v2_1_20_axi_crossbar/1
c_axi_addr_width=32 | c_axi_aruser_width=1 | c_axi_awuser_width=1 | c_axi_buser_width=1
c_axi_data_width=32 | c_axi_id_width=1 | c_axi_protocol=2 | c_axi_ruser_width=1
c_axi_supports_user_signals=0 | c_axi_wuser_width=1 | c_connectivity_mode=0 | c_family=zynq
c_m_axi_addr_width=0x000000100000000c0000000c000000100000000c00000010 | c_m_axi_base_addr=0x0000000041200000000000007c420000000000007c400000000000007902000000000000416000000000000045000000 | c_m_axi_read_connectivity=0x000000010000000100000001000000010000000100000001 | c_m_axi_read_issuing=0x000000010000000100000001000000010000000100000001
c_m_axi_secure=0x000000000000000000000000000000000000000000000000 | c_m_axi_write_connectivity=0x000000010000000100000001000000010000000100000001 | c_m_axi_write_issuing=0x000000010000000100000001000000010000000100000001 | c_num_addr_ranges=1
c_num_master_slots=6 | c_num_slave_slots=1 | c_r_register=1 | c_s_axi_arb_priority=0x00000000
c_s_axi_base_id=0x00000000 | c_s_axi_read_acceptance=0x00000001 | c_s_axi_single_thread=0x00000001 | c_s_axi_thread_id_width=0x00000000
c_s_axi_write_acceptance=0x00000001 | core_container=NA | iptotal=1 | x_ipcorerevision=20
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=axi_crossbar | x_ipproduct=Vivado 2019.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=2.1
axi_iic/1
c_default_value=0x00 | c_family=zynq | c_gpo_width=1 | c_iic_freq=100000
c_s_axi_aclk_freq_hz=100000000 | c_s_axi_addr_width=9 | c_s_axi_data_width=32 | c_scl_inertial_delay=0
c_sda_inertial_delay=0 | c_sda_level=1 | c_smbus_pmbus_host=0 | c_ten_bit_adr=0
core_container=NA | iptotal=1 | x_ipcorerevision=22 | x_iplanguage=VERILOG
x_iplibrary=ip | x_ipname=axi_iic | x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=2.0
axi_protocol_converter_v2_1_19_axi_protocol_converter/1
c_axi_addr_width=32 | c_axi_aruser_width=1 | c_axi_awuser_width=1 | c_axi_buser_width=1
c_axi_data_width=32 | c_axi_id_width=12 | c_axi_ruser_width=1 | c_axi_supports_read=1
c_axi_supports_user_signals=0 | c_axi_supports_write=1 | c_axi_wuser_width=1 | c_family=zynq
c_ignore_id=0 | c_m_axi_protocol=2 | c_s_axi_protocol=1 | c_translation_mode=2
core_container=NA | iptotal=1 | x_ipcorerevision=19 | x_iplanguage=VERILOG
x_iplibrary=ip | x_ipname=axi_protocol_converter | x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=2.1
bd_31bd/1
advanced_properties=0 | component_name=system_axi_hp1_interconnect_0 | core_container=NA | has_aresetn=1
iptotal=1 | num_clks=1 | num_mi=1 | num_si=1
x_ipcorerevision=11 | x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=smartconnect
x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
bd_c0fd/1
advanced_properties=0 | component_name=system_axi_hp2_interconnect_0 | core_container=NA | has_aresetn=1
iptotal=1 | num_clks=1 | num_mi=1 | num_si=1
x_ipcorerevision=11 | x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=smartconnect
x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
proc_sys_reset/1
c_aux_reset_high=0 | c_aux_rst_width=4 | c_ext_reset_high=0 | c_ext_rst_width=1
c_family=zynq | c_num_bus_rst=1 | c_num_interconnect_aresetn=1 | c_num_perp_aresetn=1
c_num_perp_rst=1 | core_container=NA | iptotal=1 | x_ipcorerevision=13
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=proc_sys_reset | x_ipproduct=Vivado 2019.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=5.0
proc_sys_reset/2
c_aux_reset_high=0 | c_aux_rst_width=4 | c_ext_reset_high=0 | c_ext_rst_width=4
c_family=zynq | c_num_bus_rst=1 | c_num_interconnect_aresetn=1 | c_num_perp_aresetn=1
c_num_perp_rst=1 | core_container=NA | iptotal=1 | x_ipcorerevision=13
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=proc_sys_reset | x_ipproduct=Vivado 2019.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=5.0
processing_system7_v5.5_user_configuration/1
core_container=NA | iptotal=1 | pcw_apu_clk_ratio_enable=6:2:1 | pcw_apu_peripheral_freqmhz=666.666666
pcw_armpll_ctrl_fbdiv=40 | pcw_can0_grp_clk_enable=0 | pcw_can0_peripheral_clksrc=External | pcw_can0_peripheral_enable=0
pcw_can0_peripheral_freqmhz=-1 | pcw_can1_grp_clk_enable=0 | pcw_can1_peripheral_clksrc=External | pcw_can1_peripheral_enable=0
pcw_can1_peripheral_freqmhz=-1 | pcw_can_peripheral_clksrc=IO PLL | pcw_can_peripheral_freqmhz=100 | pcw_cpu_cpu_pll_freqmhz=1333.333
pcw_cpu_peripheral_clksrc=ARM PLL | pcw_crystal_peripheral_freqmhz=33.333333 | pcw_dci_peripheral_clksrc=DDR PLL | pcw_dci_peripheral_freqmhz=10.159
pcw_ddr_ddr_pll_freqmhz=1066.667 | pcw_ddr_hpr_to_critical_priority_level=15 | pcw_ddr_hprlpr_queue_partition=HPR(0)/LPR(32) | pcw_ddr_lpr_to_critical_priority_level=2
pcw_ddr_peripheral_clksrc=DDR PLL | pcw_ddr_port0_hpr_enable=0 | pcw_ddr_port1_hpr_enable=0 | pcw_ddr_port2_hpr_enable=0
pcw_ddr_port3_hpr_enable=0 | pcw_ddr_write_to_critical_priority_level=2 | pcw_ddrpll_ctrl_fbdiv=32 | pcw_enet0_enet0_io=MIO 16 .. 27
pcw_enet0_grp_mdio_enable=1 | pcw_enet0_peripheral_clksrc=IO PLL | pcw_enet0_peripheral_enable=1 | pcw_enet0_peripheral_freqmhz=1000 Mbps
pcw_enet0_reset_enable=1 | pcw_enet0_reset_io=MIO 51 | pcw_enet1_enet1_io=MIO 28 .. 39 | pcw_enet1_grp_mdio_enable=0
pcw_enet1_peripheral_clksrc=External | pcw_enet1_peripheral_enable=1 | pcw_enet1_peripheral_freqmhz=1000 Mbps | pcw_enet1_reset_enable=0
pcw_enet_reset_polarity=Active Low | pcw_fclk0_peripheral_clksrc=IO PLL | pcw_fclk1_peripheral_clksrc=IO PLL | pcw_fclk2_peripheral_clksrc=IO PLL
pcw_fclk3_peripheral_clksrc=IO PLL | pcw_fpga0_peripheral_freqmhz=100.0 | pcw_fpga1_peripheral_freqmhz=200.0 | pcw_fpga2_peripheral_freqmhz=200.0
pcw_fpga3_peripheral_freqmhz=50 | pcw_fpga_fclk0_enable=1 | pcw_fpga_fclk1_enable=1 | pcw_fpga_fclk2_enable=1
pcw_fpga_fclk3_enable=0 | pcw_gpio_emio_gpio_enable=1 | pcw_gpio_emio_gpio_io=64 | pcw_gpio_mio_gpio_enable=1
pcw_gpio_mio_gpio_io=MIO | pcw_gpio_peripheral_enable=0 | pcw_i2c0_grp_int_enable=0 | pcw_i2c0_peripheral_enable=0
pcw_i2c0_reset_enable=0 | pcw_i2c1_grp_int_enable=0 | pcw_i2c1_peripheral_enable=0 | pcw_i2c1_reset_enable=0
pcw_i2c_reset_polarity=Active Low | pcw_io_io_pll_freqmhz=1000.000 | pcw_iopll_ctrl_fbdiv=30 | pcw_irq_f2p_mode=REVERSE
pcw_m_axi_gp0_freqmhz=100 | pcw_m_axi_gp1_freqmhz=10 | pcw_nand_cycles_t_ar=1 | pcw_nand_cycles_t_clr=1
pcw_nand_cycles_t_rc=11 | pcw_nand_cycles_t_rea=1 | pcw_nand_cycles_t_rr=1 | pcw_nand_cycles_t_wc=11
pcw_nand_cycles_t_wp=1 | pcw_nand_grp_d8_enable=0 | pcw_nand_nand_io=MIO 0 2.. 14 | pcw_nand_peripheral_enable=1
pcw_nor_cs0_t_ceoe=1 | pcw_nor_cs0_t_pc=1 | pcw_nor_cs0_t_rc=11 | pcw_nor_cs0_t_tr=1
pcw_nor_cs0_t_wc=11 | pcw_nor_cs0_t_wp=1 | pcw_nor_cs0_we_time=0 | pcw_nor_cs1_t_ceoe=1
pcw_nor_cs1_t_pc=1 | pcw_nor_cs1_t_rc=11 | pcw_nor_cs1_t_tr=1 | pcw_nor_cs1_t_wc=11
pcw_nor_cs1_t_wp=1 | pcw_nor_cs1_we_time=0 | pcw_nor_grp_a25_enable=0 | pcw_nor_grp_cs0_enable=0
pcw_nor_grp_cs1_enable=0 | pcw_nor_grp_sram_cs0_enable=0 | pcw_nor_grp_sram_cs1_enable=0 | pcw_nor_grp_sram_int_enable=0
pcw_nor_peripheral_enable=0 | pcw_nor_sram_cs0_t_ceoe=1 | pcw_nor_sram_cs0_t_pc=1 | pcw_nor_sram_cs0_t_rc=11
pcw_nor_sram_cs0_t_tr=1 | pcw_nor_sram_cs0_t_wc=11 | pcw_nor_sram_cs0_t_wp=1 | pcw_nor_sram_cs0_we_time=0
pcw_nor_sram_cs1_t_ceoe=1 | pcw_nor_sram_cs1_t_pc=1 | pcw_nor_sram_cs1_t_rc=11 | pcw_nor_sram_cs1_t_tr=1
pcw_nor_sram_cs1_t_wc=11 | pcw_nor_sram_cs1_t_wp=1 | pcw_nor_sram_cs1_we_time=0 | pcw_override_basic_clock=0
pcw_pcap_peripheral_clksrc=IO PLL | pcw_pcap_peripheral_freqmhz=200 | pcw_pjtag_peripheral_enable=0 | pcw_preset_bank0_voltage=LVCMOS 3.3V
pcw_preset_bank1_voltage=LVCMOS 1.8V | pcw_qspi_grp_fbclk_enable=0 | pcw_qspi_grp_io1_enable=0 | pcw_qspi_grp_single_ss_enable=0
pcw_qspi_grp_ss1_enable=0 | pcw_qspi_internal_highaddress=0xFCFFFFFF | pcw_qspi_peripheral_clksrc=IO PLL | pcw_qspi_peripheral_enable=0
pcw_qspi_peripheral_freqmhz=200 | pcw_s_axi_acp_freqmhz=10 | pcw_s_axi_gp0_freqmhz=10 | pcw_s_axi_gp1_freqmhz=10
pcw_s_axi_hp0_data_width=64 | pcw_s_axi_hp0_freqmhz=10 | pcw_s_axi_hp1_data_width=64 | pcw_s_axi_hp1_freqmhz=100
pcw_s_axi_hp2_data_width=64 | pcw_s_axi_hp2_freqmhz=100 | pcw_s_axi_hp3_data_width=64 | pcw_s_axi_hp3_freqmhz=10
pcw_sd0_grp_cd_enable=1 | pcw_sd0_grp_cd_io=MIO 50 | pcw_sd0_grp_pow_enable=0 | pcw_sd0_grp_wp_enable=0
pcw_sd0_peripheral_enable=1 | pcw_sd0_sd0_io=MIO 40 .. 45 | pcw_sd1_grp_cd_enable=0 | pcw_sd1_grp_pow_enable=0
pcw_sd1_grp_wp_enable=0 | pcw_sd1_peripheral_enable=0 | pcw_sdio_peripheral_clksrc=IO PLL | pcw_sdio_peripheral_freqmhz=50
pcw_smc_peripheral_clksrc=IO PLL | pcw_smc_peripheral_freqmhz=100 | pcw_spi0_grp_ss0_enable=1 | pcw_spi0_grp_ss0_io=EMIO
pcw_spi0_grp_ss1_enable=1 | pcw_spi0_grp_ss1_io=EMIO | pcw_spi0_grp_ss2_enable=1 | pcw_spi0_grp_ss2_io=EMIO
pcw_spi0_peripheral_enable=1 | pcw_spi0_spi0_io=EMIO | pcw_spi1_grp_ss0_enable=1 | pcw_spi1_grp_ss0_io=EMIO
pcw_spi1_grp_ss1_enable=1 | pcw_spi1_grp_ss1_io=EMIO | pcw_spi1_grp_ss2_enable=1 | pcw_spi1_grp_ss2_io=EMIO
pcw_spi1_peripheral_enable=1 | pcw_spi1_spi1_io=EMIO | pcw_spi_peripheral_clksrc=IO PLL | pcw_spi_peripheral_freqmhz=166.666666
pcw_tpiu_peripheral_clksrc=External | pcw_tpiu_peripheral_freqmhz=200 | pcw_trace_grp_16bit_enable=0 | pcw_trace_grp_2bit_enable=0
pcw_trace_grp_32bit_enable=0 | pcw_trace_grp_4bit_enable=0 | pcw_trace_grp_8bit_enable=0 | pcw_trace_peripheral_enable=0
pcw_ttc0_clk0_peripheral_clksrc=CPU_1X | pcw_ttc0_clk0_peripheral_freqmhz=133.333333 | pcw_ttc0_clk1_peripheral_clksrc=CPU_1X | pcw_ttc0_clk1_peripheral_freqmhz=133.333333
pcw_ttc0_clk2_peripheral_clksrc=CPU_1X | pcw_ttc0_clk2_peripheral_freqmhz=133.333333 | pcw_ttc0_peripheral_enable=0 | pcw_ttc1_clk0_peripheral_clksrc=CPU_1X
pcw_ttc1_clk0_peripheral_freqmhz=133.333333 | pcw_ttc1_clk1_peripheral_clksrc=CPU_1X | pcw_ttc1_clk1_peripheral_freqmhz=133.333333 | pcw_ttc1_clk2_peripheral_clksrc=CPU_1X
pcw_ttc1_clk2_peripheral_freqmhz=133.333333 | pcw_ttc1_peripheral_enable=0 | pcw_ttc_peripheral_freqmhz=50 | pcw_uart0_baud_rate=115200
pcw_uart0_grp_full_enable=0 | pcw_uart0_peripheral_enable=1 | pcw_uart0_uart0_io=MIO 46 .. 47 | pcw_uart1_baud_rate=115200
pcw_uart1_grp_full_enable=0 | pcw_uart1_peripheral_enable=1 | pcw_uart1_uart1_io=MIO 48 .. 49 | pcw_uart_peripheral_clksrc=IO PLL
pcw_uart_peripheral_freqmhz=100 | pcw_uiparam_ddr_adv_enable=0 | pcw_uiparam_ddr_al=0 | pcw_uiparam_ddr_bank_addr_count=3
pcw_uiparam_ddr_bl=8 | pcw_uiparam_ddr_board_delay0=0.264 | pcw_uiparam_ddr_board_delay1=0.265 | pcw_uiparam_ddr_board_delay2=0.330
pcw_uiparam_ddr_board_delay3=0.330 | pcw_uiparam_ddr_bus_width=32 Bit | pcw_uiparam_ddr_cl=7 | pcw_uiparam_ddr_clock_0_length_mm=0
pcw_uiparam_ddr_clock_0_package_length=137.1865 | pcw_uiparam_ddr_clock_0_propogation_delay=160 | pcw_uiparam_ddr_clock_1_length_mm=0 | pcw_uiparam_ddr_clock_1_package_length=137.1865
pcw_uiparam_ddr_clock_1_propogation_delay=160 | pcw_uiparam_ddr_clock_2_length_mm=0 | pcw_uiparam_ddr_clock_2_package_length=137.1865 | pcw_uiparam_ddr_clock_2_propogation_delay=160
pcw_uiparam_ddr_clock_3_length_mm=0 | pcw_uiparam_ddr_clock_3_package_length=137.1865 | pcw_uiparam_ddr_clock_3_propogation_delay=160 | pcw_uiparam_ddr_clock_stop_en=0
pcw_uiparam_ddr_col_addr_count=10 | pcw_uiparam_ddr_cwl=6 | pcw_uiparam_ddr_device_capacity=4096 MBits | pcw_uiparam_ddr_dq_0_length_mm=0
pcw_uiparam_ddr_dq_0_package_length=104.762 | pcw_uiparam_ddr_dq_0_propogation_delay=160 | pcw_uiparam_ddr_dq_1_length_mm=0 | pcw_uiparam_ddr_dq_1_package_length=122.158
pcw_uiparam_ddr_dq_1_propogation_delay=160 | pcw_uiparam_ddr_dq_2_length_mm=0 | pcw_uiparam_ddr_dq_2_package_length=124.95 | pcw_uiparam_ddr_dq_2_propogation_delay=160
pcw_uiparam_ddr_dq_3_length_mm=0 | pcw_uiparam_ddr_dq_3_package_length=143.8565 | pcw_uiparam_ddr_dq_3_propogation_delay=160 | pcw_uiparam_ddr_dqs_0_length_mm=0
pcw_uiparam_ddr_dqs_0_package_length=97.9265 | pcw_uiparam_ddr_dqs_0_propogation_delay=160 | pcw_uiparam_ddr_dqs_1_length_mm=0 | pcw_uiparam_ddr_dqs_1_package_length=119.8725
pcw_uiparam_ddr_dqs_1_propogation_delay=160 | pcw_uiparam_ddr_dqs_2_length_mm=0 | pcw_uiparam_ddr_dqs_2_package_length=119.076 | pcw_uiparam_ddr_dqs_2_propogation_delay=160
pcw_uiparam_ddr_dqs_3_length_mm=0 | pcw_uiparam_ddr_dqs_3_package_length=140.8255 | pcw_uiparam_ddr_dqs_3_propogation_delay=160 | pcw_uiparam_ddr_dqs_to_clk_delay_0=-0.053
pcw_uiparam_ddr_dqs_to_clk_delay_1=-0.059 | pcw_uiparam_ddr_dqs_to_clk_delay_2=0.065 | pcw_uiparam_ddr_dqs_to_clk_delay_3=0.066 | pcw_uiparam_ddr_dram_width=16 Bits
pcw_uiparam_ddr_ecc=Disabled | pcw_uiparam_ddr_enable=1 | pcw_uiparam_ddr_freq_mhz=533.333333 | pcw_uiparam_ddr_high_temp=Normal (0-85)
pcw_uiparam_ddr_memory_type=DDR 3 | pcw_uiparam_ddr_partno=MT41K256M16 RE-125 | pcw_uiparam_ddr_row_addr_count=15 | pcw_uiparam_ddr_speed_bin=DDR3_1066F
pcw_uiparam_ddr_t_faw=40.0 | pcw_uiparam_ddr_t_ras_min=35.0 | pcw_uiparam_ddr_t_rc=48.75 | pcw_uiparam_ddr_t_rcd=7
pcw_uiparam_ddr_t_rp=7 | pcw_uiparam_ddr_train_data_eye=1 | pcw_uiparam_ddr_train_read_gate=1 | pcw_uiparam_ddr_train_write_level=1
pcw_uiparam_ddr_use_internal_vref=0 | pcw_usb0_peripheral_enable=0 | pcw_usb0_peripheral_freqmhz=60 | pcw_usb0_reset_enable=0
pcw_usb1_peripheral_enable=0 | pcw_usb1_peripheral_freqmhz=60 | pcw_usb1_reset_enable=0 | pcw_usb_reset_polarity=Active Low
pcw_use_cross_trigger=0 | pcw_use_m_axi_gp0=1 | pcw_use_m_axi_gp1=0 | pcw_use_s_axi_acp=0
pcw_use_s_axi_gp0=0 | pcw_use_s_axi_gp1=0 | pcw_use_s_axi_hp0=0 | pcw_use_s_axi_hp1=1
pcw_use_s_axi_hp2=1 | pcw_use_s_axi_hp3=0 | pcw_wdt_peripheral_clksrc=CPU_1X | pcw_wdt_peripheral_enable=0
pcw_wdt_peripheral_freqmhz=133.333333
processing_system7_v5_5_processing_system7/1
c_dm_width=4 | c_dq_width=32 | c_dqs_width=4 | c_emio_gpio_width=64
c_en_emio_enet0=0 | c_en_emio_enet1=0 | c_en_emio_pjtag=0 | c_en_emio_trace=0
c_fclk_clk0_buf=TRUE | c_fclk_clk1_buf=TRUE | c_fclk_clk2_buf=TRUE | c_fclk_clk3_buf=FALSE
c_gp0_en_modifiable_txn=1 | c_gp1_en_modifiable_txn=1 | c_include_acp_trans_check=0 | c_include_trace_buffer=0
c_irq_f2p_mode=REVERSE | c_m_axi_gp0_enable_static_remap=0 | c_m_axi_gp0_id_width=12 | c_m_axi_gp0_thread_id_width=12
c_m_axi_gp1_enable_static_remap=0 | c_m_axi_gp1_id_width=12 | c_m_axi_gp1_thread_id_width=12 | c_mio_primitive=54
c_num_f2p_intr_inputs=16 | c_package_name=ffg900 | c_ps7_si_rev=PRODUCTION | c_s_axi_acp_aruser_val=31
c_s_axi_acp_awuser_val=31 | c_s_axi_acp_id_width=3 | c_s_axi_gp0_id_width=6 | c_s_axi_gp1_id_width=6
c_s_axi_hp0_data_width=64 | c_s_axi_hp0_id_width=6 | c_s_axi_hp1_data_width=64 | c_s_axi_hp1_id_width=6
c_s_axi_hp2_data_width=64 | c_s_axi_hp2_id_width=6 | c_s_axi_hp3_data_width=64 | c_s_axi_hp3_id_width=6
c_trace_buffer_clock_delay=12 | c_trace_buffer_fifo_size=128 | c_trace_internal_width=2 | c_trace_pipeline_width=8
c_use_axi_nonsecure=0 | c_use_default_acp_user_val=0 | c_use_m_axi_gp0=1 | c_use_m_axi_gp1=0
c_use_s_axi_acp=0 | c_use_s_axi_gp0=0 | c_use_s_axi_gp1=0 | c_use_s_axi_hp0=0
c_use_s_axi_hp1=1 | c_use_s_axi_hp2=1 | c_use_s_axi_hp3=0 | core_container=NA
iptotal=1 | use_trace_data_edge_detector=0 | x_ipcorerevision=6 | x_iplanguage=VERILOG
x_iplibrary=ip | x_ipname=processing_system7 | x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=5.5
sc_exit_v1_0_8_top/1
c_addr_width=32 | c_enable_pipelining=0x1 | c_family=zynq | c_has_lock=0
c_is_cascaded=0 | c_m_aruser_width=0 | c_m_awuser_width=0 | c_m_buser_width=0
c_m_id_width=0 | c_m_limit_read_length=16 | c_m_limit_write_length=16 | c_m_protocol=1
c_m_ruser_bits_per_byte=0 | c_m_ruser_width=0 | c_m_wuser_bits_per_byte=0 | c_m_wuser_width=0
c_max_ruser_bits_per_byte=0 | c_max_wuser_bits_per_byte=0 | c_mep_identifier_width=1 | c_num_msc=1
c_num_read_outstanding=0 | c_num_write_outstanding=8 | c_rdata_width=64 | c_read_acceptance=32
c_s_id_width=1 | c_single_issuing=0 | c_ssc_route_array=0b01 | c_ssc_route_width=1
c_wdata_width=64 | c_write_acceptance=32 | core_container=NA | iptotal=1
x_ipcorerevision=8 | x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=sc_exit
x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
sc_exit_v1_0_8_top/2
c_addr_width=32 | c_enable_pipelining=0x1 | c_family=zynq | c_has_lock=0
c_is_cascaded=0 | c_m_aruser_width=0 | c_m_awuser_width=0 | c_m_buser_width=0
c_m_id_width=0 | c_m_limit_read_length=16 | c_m_limit_write_length=16 | c_m_protocol=1
c_m_ruser_bits_per_byte=0 | c_m_ruser_width=0 | c_m_wuser_bits_per_byte=0 | c_m_wuser_width=0
c_max_ruser_bits_per_byte=0 | c_max_wuser_bits_per_byte=0 | c_mep_identifier_width=1 | c_num_msc=1
c_num_read_outstanding=8 | c_num_write_outstanding=0 | c_rdata_width=64 | c_read_acceptance=32
c_s_id_width=1 | c_single_issuing=0 | c_ssc_route_array=0b10 | c_ssc_route_width=1
c_wdata_width=64 | c_write_acceptance=32 | core_container=NA | iptotal=1
x_ipcorerevision=8 | x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=sc_exit
x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
sc_mmu_v1_0_7_top/1
c_addr_width=30 | c_enable_pipelining=0x1 | c_family=zynq | c_id_width=0
c_is_cascaded=0 | c_msc_route_array=0b1 | c_msc_route_width=1 | c_num_msc=1
c_num_read_outstanding=0 | c_num_seg=1 | c_num_write_outstanding=8 | c_rdata_width=64
c_read_acceptance=32 | c_s_aruser_width=0 | c_s_awuser_width=0 | c_s_buser_width=0
c_s_protocol=1 | c_s_ruser_width=0 | c_s_wuser_width=0 | c_seg_base_addr_array=0x0000000000000000
c_seg_secure_read_array=0b0 | c_seg_secure_write_array=0b0 | c_seg_sep_route_array=0x0000000000000000 | c_seg_size_array=0x0000001e
c_seg_supports_read_array=0x1 | c_seg_supports_write_array=0x1 | c_single_issuing=0 | c_supports_narrow=0
c_supports_read_decerr=1 | c_supports_wrap=1 | c_supports_write_decerr=0 | c_wdata_width=64
c_write_acceptance=32 | core_container=NA | iptotal=1 | x_ipcorerevision=7
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=sc_mmu | x_ipproduct=Vivado 2019.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
sc_mmu_v1_0_7_top/2
c_addr_width=30 | c_enable_pipelining=0x1 | c_family=zynq | c_id_width=0
c_is_cascaded=0 | c_msc_route_array=0b1 | c_msc_route_width=1 | c_num_msc=1
c_num_read_outstanding=8 | c_num_seg=1 | c_num_write_outstanding=0 | c_rdata_width=64
c_read_acceptance=32 | c_s_aruser_width=0 | c_s_awuser_width=0 | c_s_buser_width=0
c_s_protocol=1 | c_s_ruser_width=0 | c_s_wuser_width=0 | c_seg_base_addr_array=0x0000000000000000
c_seg_secure_read_array=0b0 | c_seg_secure_write_array=0b0 | c_seg_sep_route_array=0x0000000000000000 | c_seg_size_array=0x0000001e
c_seg_supports_read_array=0x1 | c_seg_supports_write_array=0x1 | c_single_issuing=0 | c_supports_narrow=0
c_supports_read_decerr=0 | c_supports_wrap=1 | c_supports_write_decerr=1 | c_wdata_width=64
c_write_acceptance=32 | core_container=NA | iptotal=1 | x_ipcorerevision=7
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=sc_mmu | x_ipproduct=Vivado 2019.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0
sc_node_v1_0_10_top/1
c_aclk_relationship=1 | c_aclken_conversion=0 | c_addr_width=30 | c_arbiter_mode=1
c_channel=3 | c_disable_ip=0 | c_enable_pipelining=0x01 | c_family=zynq
c_fifo_ip=0 | c_fifo_output_reg=1 | c_fifo_size=5 | c_fifo_type=0
c_id_width=1 | c_m_num_bytes_array=0x00000008 | c_m_pipeline=0 | c_m_send_pipeline=0
c_max_payld_bytes=8 | c_num_mi=1 | c_num_outstanding=8 | c_num_si=1
c_payld_width=136 | c_s_latency=0 | c_s_num_bytes_array=0x00000008 | c_s_pipeline=0
c_sc_route_width=1 | c_synchronization_stages=3 | c_user_bits_per_byte=0 | c_user_width=0
core_container=NA | iptotal=1 | x_ipcorerevision=10 | x_iplanguage=VERILOG
x_iplibrary=ip | x_ipname=sc_node | x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=1.0
sc_node_v1_0_10_top/2
c_aclk_relationship=1 | c_aclken_conversion=0 | c_addr_width=30 | c_arbiter_mode=1
c_channel=4 | c_disable_ip=0 | c_enable_pipelining=0x01 | c_family=zynq
c_fifo_ip=0 | c_fifo_output_reg=1 | c_fifo_size=5 | c_fifo_type=0
c_id_width=1 | c_m_num_bytes_array=0x00000008 | c_m_pipeline=0 | c_m_send_pipeline=0
c_max_payld_bytes=8 | c_num_mi=1 | c_num_outstanding=8 | c_num_si=1
c_payld_width=5 | c_s_latency=0 | c_s_num_bytes_array=0x00000008 | c_s_pipeline=0
c_sc_route_width=1 | c_synchronization_stages=3 | c_user_bits_per_byte=0 | c_user_width=0
core_container=NA | iptotal=1 | x_ipcorerevision=10 | x_iplanguage=VERILOG
x_iplibrary=ip | x_ipname=sc_node | x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=1.0
sc_node_v1_0_10_top/3
c_aclk_relationship=1 | c_aclken_conversion=0 | c_addr_width=30 | c_arbiter_mode=1
c_channel=1 | c_disable_ip=0 | c_enable_pipelining=0x01 | c_family=zynq
c_fifo_ip=0 | c_fifo_output_reg=1 | c_fifo_size=5 | c_fifo_type=0
c_id_width=1 | c_m_num_bytes_array=0x00000008 | c_m_pipeline=0 | c_m_send_pipeline=0
c_max_payld_bytes=8 | c_num_mi=1 | c_num_outstanding=8 | c_num_si=1
c_payld_width=88 | c_s_latency=0 | c_s_num_bytes_array=0x00000008 | c_s_pipeline=0
c_sc_route_width=1 | c_synchronization_stages=3 | c_user_bits_per_byte=0 | c_user_width=512
core_container=NA | iptotal=1 | x_ipcorerevision=10 | x_iplanguage=VERILOG
x_iplibrary=ip | x_ipname=sc_node | x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=1.0
sc_node_v1_0_10_top/4
c_aclk_relationship=1 | c_aclken_conversion=0 | c_addr_width=30 | c_arbiter_mode=1
c_channel=2 | c_disable_ip=0 | c_enable_pipelining=0x01 | c_family=zynq
c_fifo_ip=0 | c_fifo_output_reg=1 | c_fifo_size=5 | c_fifo_type=0
c_id_width=1 | c_m_num_bytes_array=0x00000008 | c_m_pipeline=0 | c_m_send_pipeline=0
c_max_payld_bytes=8 | c_num_mi=1 | c_num_outstanding=8 | c_num_si=1
c_payld_width=136 | c_s_latency=0 | c_s_num_bytes_array=0x00000008 | c_s_pipeline=0
c_sc_route_width=1 | c_synchronization_stages=3 | c_user_bits_per_byte=0 | c_user_width=0
core_container=NA | iptotal=1 | x_ipcorerevision=10 | x_iplanguage=VERILOG
x_iplibrary=ip | x_ipname=sc_node | x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=1.0
sc_node_v1_0_10_top/5
c_aclk_relationship=1 | c_aclken_conversion=0 | c_addr_width=30 | c_arbiter_mode=1
c_channel=0 | c_disable_ip=0 | c_enable_pipelining=0x01 | c_family=zynq
c_fifo_ip=0 | c_fifo_output_reg=1 | c_fifo_size=5 | c_fifo_type=0
c_id_width=1 | c_m_num_bytes_array=0x00000008 | c_m_pipeline=0 | c_m_send_pipeline=0
c_max_payld_bytes=8 | c_num_mi=1 | c_num_outstanding=8 | c_num_si=1
c_payld_width=83 | c_s_latency=0 | c_s_num_bytes_array=0x00000008 | c_s_pipeline=0
c_sc_route_width=1 | c_synchronization_stages=3 | c_user_bits_per_byte=0 | c_user_width=512
core_container=NA | iptotal=1 | x_ipcorerevision=10 | x_iplanguage=VERILOG
x_iplibrary=ip | x_ipname=sc_node | x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=1.0
sc_si_converter_v1_0_8_top/1
c_addr_width=30 | c_enable_pipelining=0x1 | c_has_burst=0 | c_id_width=1
c_is_cascaded=0 | c_limit_read_length=0 | c_limit_write_length=0 | c_max_ruser_bits_per_byte=0
c_max_wuser_bits_per_byte=0 | c_mep_identifier_width=1 | c_msc_rdata_width_array=0x00000040 | c_msc_wdata_width_array=0x00000040
c_num_msc=1 | c_num_read_outstanding=0 | c_num_read_threads=1 | c_num_seg=1
c_num_write_outstanding=8 | c_num_write_threads=1 | c_rdata_width=64 | c_read_acceptance=32
c_read_watermark=0 | c_s_ruser_bits_per_byte=0 | c_s_wuser_bits_per_byte=0 | c_sep_protocol_array=0x00000001
c_sep_rdata_width_array=0x00000040 | c_sep_wdata_width_array=0x00000040 | c_single_issuing=0 | c_supports_narrow=0
c_wdata_width=64 | c_write_acceptance=32 | c_write_watermark=0 | core_container=NA
iptotal=1 | x_ipcorerevision=8 | x_iplanguage=VERILOG | x_iplibrary=ip
x_ipname=sc_si_converter | x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com
x_ipversion=1.0
sc_si_converter_v1_0_8_top/2
c_addr_width=30 | c_enable_pipelining=0x1 | c_has_burst=0 | c_id_width=1
c_is_cascaded=0 | c_limit_read_length=0 | c_limit_write_length=0 | c_max_ruser_bits_per_byte=0
c_max_wuser_bits_per_byte=0 | c_mep_identifier_width=1 | c_msc_rdata_width_array=0x00000040 | c_msc_wdata_width_array=0x00000040
c_num_msc=1 | c_num_read_outstanding=8 | c_num_read_threads=1 | c_num_seg=1
c_num_write_outstanding=0 | c_num_write_threads=1 | c_rdata_width=64 | c_read_acceptance=32
c_read_watermark=0 | c_s_ruser_bits_per_byte=0 | c_s_wuser_bits_per_byte=0 | c_sep_protocol_array=0x00000001
c_sep_rdata_width_array=0x00000040 | c_sep_wdata_width_array=0x00000040 | c_single_issuing=0 | c_supports_narrow=0
c_wdata_width=64 | c_write_acceptance=32 | c_write_watermark=0 | core_container=NA
iptotal=1 | x_ipcorerevision=8 | x_iplanguage=VERILOG | x_iplibrary=ip
x_ipname=sc_si_converter | x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com
x_ipversion=1.0
util_reduced_logic_v2_0_4_util_reduced_logic/1
c_operation=and | c_size=2 | core_container=NA | iptotal=1
x_ipcorerevision=4 | x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=util_reduced_logic
x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=2.0
xlconcat_v2_1_3_xlconcat/1
core_container=NA | dout_width=16 | in0_width=1 | in10_width=1
in11_width=1 | in12_width=1 | in13_width=1 | in14_width=1
in15_width=1 | in16_width=1 | in17_width=1 | in18_width=1
in19_width=1 | in1_width=1 | in20_width=1 | in21_width=1
in22_width=1 | in23_width=1 | in24_width=1 | in25_width=1
in26_width=1 | in27_width=1 | in28_width=1 | in29_width=1
in2_width=1 | in30_width=1 | in31_width=1 | in3_width=1
in4_width=1 | in5_width=1 | in6_width=1 | in7_width=1
in8_width=1 | in9_width=1 | iptotal=1 | num_ports=16
x_ipcorerevision=3 | x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=xlconcat
x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=2.1
xlconcat_v2_1_3_xlconcat/2
core_container=NA | dout_width=2 | in0_width=1 | in10_width=1
in11_width=1 | in12_width=1 | in13_width=1 | in14_width=1
in15_width=1 | in16_width=1 | in17_width=1 | in18_width=1
in19_width=1 | in1_width=1 | in20_width=1 | in21_width=1
in22_width=1 | in23_width=1 | in24_width=1 | in25_width=1
in26_width=1 | in27_width=1 | in28_width=1 | in29_width=1
in2_width=1 | in30_width=1 | in31_width=1 | in3_width=1
in4_width=1 | in5_width=1 | in6_width=1 | in7_width=1
in8_width=1 | in9_width=1 | iptotal=1 | num_ports=2
x_ipcorerevision=3 | x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=xlconcat
x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=2.1
xlconstant_v1_1_6_xlconstant/1
const_val=0x0 | const_width=1 | core_container=NA | iptotal=1
x_ipcorerevision=6 | x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=xlconstant
x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.1
xpm_memory_base/1
x_ipversion=1.1 | addr_width_a=5 | addr_width_b=5 | auto_sleep_time=0
byte_write_width_a=101 | byte_write_width_b=101 | cascade_height=0 | clocking_mode=0
core_container=NA | ecc_mode=0 | iptotal=4 | max_num_char=0
memory_optimization=true | memory_primitive=1 | memory_size=3232 | memory_type=1
message_control=0 | num_char_loc=0 | p_ecc_mode=no_ecc | p_enable_byte_write_a=0
p_enable_byte_write_b=0 | p_max_depth_data=32 | p_memory_opt=yes | p_memory_primitive=distributed
p_min_width_data=101 | p_min_width_data_a=101 | p_min_width_data_b=101 | p_min_width_data_ecc=101
p_min_width_data_ldw=4 | p_min_width_data_shft=101 | p_num_cols_write_a=1 | p_num_cols_write_b=1
p_num_rows_read_a=1 | p_num_rows_read_b=1 | p_num_rows_write_a=1 | p_num_rows_write_b=1
p_sdp_write_mode=yes | p_width_addr_lsb_read_a=0 | p_width_addr_lsb_read_b=0 | p_width_addr_lsb_write_a=0
p_width_addr_lsb_write_b=0 | p_width_addr_read_a=5 | p_width_addr_read_b=5 | p_width_addr_write_a=5
p_width_addr_write_b=5 | p_width_col_write_a=101 | p_width_col_write_b=101 | read_data_width_a=101
read_data_width_b=101 | read_latency_a=2 | read_latency_b=1 | read_reset_value_a=0
read_reset_value_b=0 | rst_mode_a=SYNC | rst_mode_b=SYNC | rsta_loop_iter=104
rstb_loop_iter=104 | sim_assert_chk=0 | use_embedded_constraint=0 | use_mem_init=0
version=0 | wakeup_time=0 | write_data_width_a=101 | write_data_width_b=101
write_mode_a=1 | write_mode_b=1
xpm_memory_sdpram/1
write_mode_b=1 | addr_width_a=5 | addr_width_b=5 | auto_sleep_time=0
byte_write_width_a=101 | cascade_height=0 | clocking_mode=0 | core_container=NA
ecc_mode=0 | iptotal=4 | memory_optimization=true | memory_primitive=1
memory_size=3232 | message_control=0 | p_clocking_mode=0 | p_ecc_mode=0
p_memory_optimization=1 | p_memory_primitive=1 | p_wakeup_time=0 | p_write_mode_b=1
read_data_width_b=101 | read_latency_b=1 | read_reset_value_b=0 | rst_mode_a=SYNC
rst_mode_b=SYNC | sim_assert_chk=0 | use_embedded_constraint=0 | use_mem_init=0
wakeup_time=0 | write_data_width_a=101 | write_mode_b=1

report_drc
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -internal=default::[not_specified] | -internal_only=default::[not_specified] | -messages=default::[not_specified]
-name=default::[not_specified] | -no_waivers=default::[not_specified] | -return_string=default::[not_specified] | -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] | -waived=default::[not_specified]
results
aval-4=24 | check-3=1 | plck-12=1 | reqp-1839=20

report_methodology
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -messages=default::[not_specified] | -name=default::[not_specified] | -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] | -waived=default::[not_specified]
results
ckbf-1=2 | lutar-1=6 | timing-10=1 | timing-17=27
timing-18=34 | timing-9=1 | xdcb-5=4

report_power
command_line_options
-advisory=default::[not_specified] | -append=default::[not_specified] | -file=[specified] | -format=default::text
-hier=default::power | -hierarchical_depth=default::4 | -l=default::[not_specified] | -name=default::[not_specified]
-no_propagation=default::[not_specified] | -return_string=default::[not_specified] | -rpx=[specified] | -verbose=default::[not_specified]
-vid=default::[not_specified] | -xpe=default::[not_specified]
usage
airflow=250 (LFM) | ambient_temp=25.0 (C) | bi-dir_toggle=12.500000 | bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) | board_selection=medium (10"x10") | bram=0.008573 | clocks=0.168118
confidence_level_clock_activity=High | confidence_level_design_state=High | confidence_level_device_models=High | confidence_level_internal_activity=Medium
confidence_level_io_activity=Low | confidence_level_overall=Low | customer=TBD | customer_class=TBD
devstatic=0.228510 | die=xc7z045ffg900-2 | dsp=0.064280 | dsp_output_toggle=12.500000
dynamic=2.335345 | effective_thetaja=1.8 | enable_probability=0.990000 | family=zynq
ff_toggle=12.500000 | flow_state=routed | heatsink=medium (Medium Profile) | i/o=0.209734
input_toggle=12.500000 | junction_temp=29.5 (C) | logic=0.183250 | mgtavcc_dynamic_current=0.000000
mgtavcc_static_current=0.000000 | mgtavcc_total_current=0.000000 | mgtavcc_voltage=1.000000 | mgtavtt_dynamic_current=0.000000
mgtavtt_static_current=0.000000 | mgtavtt_total_current=0.000000 | mgtavtt_voltage=1.200000 | mgtvccaux_dynamic_current=0.000000
mgtvccaux_static_current=0.000000 | mgtvccaux_total_current=0.000000 | mgtvccaux_voltage=1.800000 | netlist_net_matched=NA
off-chip_power=0.000000 | on-chip_power=2.563855 | output_enable=1.000000 | output_load=5.000000
output_toggle=12.500000 | package=ffg900 | pct_clock_constrained=9.000000 | pct_inputs_defined=3
platform=nt64 | process=typical | ps7=1.539066 | ram_enable=50.000000
ram_write=50.000000 | read_saif=False | set/reset_probability=0.000000 | signal_rate=False
signals=0.168405 | simulation_file=None | speedgrade=-2 | static_prob=False
temp_grade=commercial | thetajb=2.7 (C/W) | thetasa=3.3 (C/W) | toggle_rate=False
user_board_temp=25.0 (C) | user_effective_thetaja=1.8 | user_junc_temp=29.5 (C) | user_thetajb=2.7 (C/W)
user_thetasa=3.3 (C/W) | vccadc_dynamic_current=0.000000 | vccadc_static_current=0.020000 | vccadc_total_current=0.020000
vccadc_voltage=1.800000 | vccaux_dynamic_current=0.028121 | vccaux_io_dynamic_current=0.000000 | vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000 | vccaux_io_voltage=1.800000 | vccaux_static_current=0.040893 | vccaux_total_current=0.069014
vccaux_voltage=1.800000 | vccbram_dynamic_current=0.000291 | vccbram_static_current=0.002019 | vccbram_total_current=0.002310
vccbram_voltage=1.000000 | vccint_dynamic_current=0.582814 | vccint_static_current=0.061094 | vccint_total_current=0.643908
vccint_voltage=1.000000 | vcco12_dynamic_current=0.000000 | vcco12_static_current=0.000000 | vcco12_total_current=0.000000
vcco12_voltage=1.200000 | vcco135_dynamic_current=0.000000 | vcco135_static_current=0.000000 | vcco135_total_current=0.000000
vcco135_voltage=1.350000 | vcco15_dynamic_current=0.000000 | vcco15_static_current=0.000000 | vcco15_total_current=0.000000
vcco15_voltage=1.500000 | vcco18_dynamic_current=0.085582 | vcco18_static_current=0.001000 | vcco18_total_current=0.086582
vcco18_voltage=1.800000 | vcco25_dynamic_current=0.000000 | vcco25_static_current=0.000000 | vcco25_total_current=0.000000
vcco25_voltage=2.500000 | vcco33_dynamic_current=0.002578 | vcco33_static_current=0.001000 | vcco33_total_current=0.003578
vcco33_voltage=3.300000 | vcco_ddr_dynamic_current=0.456904 | vcco_ddr_static_current=0.002000 | vcco_ddr_total_current=0.458904
vcco_ddr_voltage=1.500000 | vcco_mio0_dynamic_current=0.001750 | vcco_mio0_static_current=0.001000 | vcco_mio0_total_current=0.002750
vcco_mio0_voltage=3.300000 | vcco_mio1_dynamic_current=0.002187 | vcco_mio1_static_current=0.001000 | vcco_mio1_total_current=0.003187
vcco_mio1_voltage=1.800000 | vccpaux_dynamic_current=0.051347 | vccpaux_static_current=0.010330 | vccpaux_total_current=0.061677
vccpaux_voltage=1.800000 | vccpint_dynamic_current=0.726594 | vccpint_static_current=0.018597 | vccpint_total_current=0.745191
vccpint_voltage=1.000000 | vccpll_dynamic_current=0.013878 | vccpll_static_current=0.003000 | vccpll_total_current=0.016878
vccpll_voltage=1.800000 | version=2019.1

report_utilization
clocking
bufgctrl_available=32 | bufgctrl_fixed=0 | bufgctrl_used=5 | bufgctrl_util_percentage=15.63
bufhce_available=168 | bufhce_fixed=0 | bufhce_used=0 | bufhce_util_percentage=0.00
bufio_available=32 | bufio_fixed=0 | bufio_used=0 | bufio_util_percentage=0.00
bufmrce_available=16 | bufmrce_fixed=0 | bufmrce_used=0 | bufmrce_util_percentage=0.00
bufr_available=32 | bufr_fixed=0 | bufr_used=2 | bufr_util_percentage=6.25
mmcme2_adv_available=8 | mmcme2_adv_fixed=0 | mmcme2_adv_used=0 | mmcme2_adv_util_percentage=0.00
plle2_adv_available=8 | plle2_adv_fixed=0 | plle2_adv_used=0 | plle2_adv_util_percentage=0.00
dsp
dsp48e1_only_used=28 | dsps_available=900 | dsps_fixed=0 | dsps_used=28
dsps_util_percentage=3.11
io_standard
blvds_25=0 | diff_hstl_i=0 | diff_hstl_i_18=0 | diff_hstl_i_dci=0
diff_hstl_i_dci_18=0 | diff_hstl_ii=0 | diff_hstl_ii_18=0 | diff_hstl_ii_dci=0
diff_hstl_ii_dci_18=0 | diff_hstl_ii_t_dci=0 | diff_hstl_ii_t_dci_18=0 | diff_hsul_12=0
diff_hsul_12_dci=0 | diff_mobile_ddr=0 | diff_sstl12=0 | diff_sstl12_dci=0
diff_sstl12_t_dci=0 | diff_sstl135=0 | diff_sstl135_dci=0 | diff_sstl135_r=0
diff_sstl135_t_dci=0 | diff_sstl15=1 | diff_sstl15_dci=0 | diff_sstl15_r=0
diff_sstl15_t_dci=1 | diff_sstl18_i=0 | diff_sstl18_i_dci=0 | diff_sstl18_ii=0
diff_sstl18_ii_dci=0 | diff_sstl18_ii_t_dci=0 | hslvdci_15=0 | hslvdci_18=0
hstl_i=0 | hstl_i_12=0 | hstl_i_18=0 | hstl_i_dci=0
hstl_i_dci_18=0 | hstl_ii=0 | hstl_ii_18=0 | hstl_ii_dci=0
hstl_ii_dci_18=0 | hstl_ii_t_dci=0 | hstl_ii_t_dci_18=0 | hsul_12=0
hsul_12_dci=0 | lvcmos12=0 | lvcmos15=0 | lvcmos18=1
lvcmos25=0 | lvcmos33=1 | lvdci_15=0 | lvdci_18=0
lvdci_dv2_15=0 | lvdci_dv2_18=0 | lvds=1 | lvds_25=0
lvttl=0 | mini_lvds_25=0 | mobile_ddr=0 | pci33_3=0
ppds_25=0 | rsds_25=0 | sstl12=0 | sstl12_dci=0
sstl12_t_dci=0 | sstl135=0 | sstl135_dci=0 | sstl135_r=0
sstl135_t_dci=0 | sstl15=1 | sstl15_dci=0 | sstl15_r=0
sstl15_t_dci=1 | sstl18_i=0 | sstl18_i_dci=0 | sstl18_ii=0
sstl18_ii_dci=0 | sstl18_ii_t_dci=0 | tmds_33=0
memory
block_ram_tile_available=545 | block_ram_tile_fixed=0 | block_ram_tile_used=4 | block_ram_tile_util_percentage=0.73
ramb18_available=1090 | ramb18_fixed=0 | ramb18_used=0 | ramb18_util_percentage=0.00
ramb36_fifo_available=545 | ramb36_fifo_fixed=0 | ramb36_fifo_used=4 | ramb36_fifo_util_percentage=0.73
ramb36e1_only_used=4
primitives
bibuf_functional_category=IO | bibuf_used=130 | bufg_functional_category=Clock | bufg_used=4
bufgctrl_functional_category=Clock | bufgctrl_used=1 | bufr_functional_category=Clock | bufr_used=2
carry4_functional_category=CarryLogic | carry4_used=1577 | dsp48e1_functional_category=Block Arithmetic | dsp48e1_used=28
fdce_functional_category=Flop & Latch | fdce_used=4224 | fdpe_functional_category=Flop & Latch | fdpe_used=166
fdre_functional_category=Flop & Latch | fdre_used=15189 | fdse_functional_category=Flop & Latch | fdse_used=308
ibuf_functional_category=IO | ibuf_used=25 | ibufds_functional_category=IO | ibufds_used=8
iddr_functional_category=IO | iddr_used=7 | idelayctrl_functional_category=IO | idelayctrl_used=2
idelaye2_functional_category=IO | idelaye2_used=7 | lut1_functional_category=LUT | lut1_used=656
lut2_functional_category=LUT | lut2_used=2843 | lut3_functional_category=LUT | lut3_used=4598
lut4_functional_category=LUT | lut4_used=1284 | lut5_functional_category=LUT | lut5_used=1214
lut6_functional_category=LUT | lut6_used=2757 | muxf7_functional_category=MuxFx | muxf7_used=27
muxf8_functional_category=MuxFx | muxf8_used=4 | obuf_functional_category=IO | obuf_used=11
obufds_functional_category=IO | obufds_used=8 | obuft_functional_category=IO | obuft_used=18
oddr_functional_category=IO | oddr_used=10 | odelaye2_functional_category=IO | odelaye2_used=10
ps7_functional_category=Specialized Resource | ps7_used=1 | ramb36e1_functional_category=Block Memory | ramb36e1_used=4
ramd32_functional_category=Distributed Memory | ramd32_used=354 | rams32_functional_category=Distributed Memory | rams32_used=114
srl16e_functional_category=Distributed Memory | srl16e_used=688 | srlc32e_functional_category=Distributed Memory | srlc32e_used=47
slice_logic
f7_muxes_available=109300 | f7_muxes_fixed=0 | f7_muxes_used=27 | f7_muxes_util_percentage=0.02
f8_muxes_available=54650 | f8_muxes_fixed=0 | f8_muxes_used=4 | f8_muxes_util_percentage=<0.01
lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=240 | lut_as_logic_available=218600 | lut_as_logic_fixed=0
lut_as_logic_used=11564 | lut_as_logic_util_percentage=5.29 | lut_as_memory_available=70400 | lut_as_memory_fixed=0
lut_as_memory_used=659 | lut_as_memory_util_percentage=0.94 | lut_as_shift_register_fixed=0 | lut_as_shift_register_used=419
register_as_flip_flop_available=437200 | register_as_flip_flop_fixed=0 | register_as_flip_flop_used=19887 | register_as_flip_flop_util_percentage=4.55
register_as_latch_available=437200 | register_as_latch_fixed=0 | register_as_latch_used=0 | register_as_latch_util_percentage=0.00
slice_luts_available=218600 | slice_luts_fixed=0 | slice_luts_used=12223 | slice_luts_util_percentage=5.59
slice_registers_available=437200 | slice_registers_fixed=0 | slice_registers_used=19887 | slice_registers_util_percentage=4.55
lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=240 | lut_as_logic_available=218600 | lut_as_logic_fixed=0
lut_as_logic_used=11564 | lut_as_logic_util_percentage=5.29 | lut_as_memory_available=70400 | lut_as_memory_fixed=0
lut_as_memory_used=659 | lut_as_memory_util_percentage=0.94 | lut_as_shift_register_fixed=0 | lut_as_shift_register_used=419
lut_in_front_of_the_register_is_unused_fixed=419 | lut_in_front_of_the_register_is_unused_used=7727 | lut_in_front_of_the_register_is_used_fixed=7727 | lut_in_front_of_the_register_is_used_used=2223
register_driven_from_outside_the_slice_fixed=2223 | register_driven_from_outside_the_slice_used=9950 | register_driven_from_within_the_slice_fixed=9950 | register_driven_from_within_the_slice_used=9937
slice_available=54650 | slice_fixed=0 | slice_registers_available=437200 | slice_registers_fixed=0
slice_registers_used=19887 | slice_registers_util_percentage=4.55 | slice_used=6664 | slice_util_percentage=12.19
slicel_fixed=0 | slicel_used=4451 | slicem_fixed=0 | slicem_used=2213
unique_control_sets_available=54650 | unique_control_sets_fixed=54650 | unique_control_sets_used=461 | unique_control_sets_util_percentage=0.84
using_o5_and_o6_fixed=0.84 | using_o5_and_o6_used=316 | using_o5_output_only_fixed=316 | using_o5_output_only_used=2
using_o6_output_only_fixed=2 | using_o6_output_only_used=101
specific_feature
bscane2_available=4 | bscane2_fixed=0 | bscane2_used=0 | bscane2_util_percentage=0.00
capturee2_available=1 | capturee2_fixed=0 | capturee2_used=0 | capturee2_util_percentage=0.00
dna_port_available=1 | dna_port_fixed=0 | dna_port_used=0 | dna_port_util_percentage=0.00
efuse_usr_available=1 | efuse_usr_fixed=0 | efuse_usr_used=0 | efuse_usr_util_percentage=0.00
frame_ecce2_available=1 | frame_ecce2_fixed=0 | frame_ecce2_used=0 | frame_ecce2_util_percentage=0.00
icape2_available=2 | icape2_fixed=0 | icape2_used=0 | icape2_util_percentage=0.00
pcie_2_1_available=1 | pcie_2_1_fixed=0 | pcie_2_1_used=0 | pcie_2_1_util_percentage=0.00
startupe2_available=1 | startupe2_fixed=0 | startupe2_used=0 | startupe2_util_percentage=0.00
xadc_available=1 | xadc_fixed=0 | xadc_used=0 | xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] | -bufg=default::12 | -cascade_dsp=default::auto | -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto | -directive=default::default | -fanout_limit=default::10000 | -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto | -gated_clock_conversion=default::off | -generic=default::[not_specified] | -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] | -max_bram=default::-1 | -max_bram_cascade_height=default::-1 | -max_dsp=default::-1
-max_uram=default::-1 | -max_uram_cascade_height=default::-1 | -mode=default::default | -name=default::[not_specified]
-no_lc=default::[not_specified] | -no_srlextract=default::[not_specified] | -no_timing_driven=default::[not_specified] | -part=xc7z045ffg900-2
-resource_sharing=default::auto | -retiming=default::[not_specified] | -rtl=default::[not_specified] | -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] | -seu_protect=default::none | -sfcu=default::[not_specified] | -shreg_min_size=default::3
-top=system_top | -verilog_define=default::[not_specified]
usage
elapsed=00:02:52s | hls_ip=0 | memory_gain=1667.594MB | memory_peak=2090.242MB