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// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 3

(* X_CORE_INFO = "xlconcat_v2_1_3_xlconcat,Vivado 2019.1" *)
(* CHECK_LICENSE_TYPE = "system_sys_concat_intc_0,xlconcat_v2_1_3_xlconcat,{}" *)
(* CORE_GENERATION_INFO = "system_sys_concat_intc_0,xlconcat_v2_1_3_xlconcat,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,I\
N23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=16,NUM_PORTS=16}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_sys_concat_intc_0 (
  In0,
  In1,
  In2,
  In3,
  In4,
  In5,
  In6,
  In7,
  In8,
  In9,
  In10,
  In11,
  In12,
  In13,
  In14,
  In15,
  dout
);

input wire [0 : 0] In0;
input wire [0 : 0] In1;
input wire [0 : 0] In2;
input wire [0 : 0] In3;
input wire [0 : 0] In4;
input wire [0 : 0] In5;
input wire [0 : 0] In6;
input wire [0 : 0] In7;
input wire [0 : 0] In8;
input wire [0 : 0] In9;
input wire [0 : 0] In10;
input wire [0 : 0] In11;
input wire [0 : 0] In12;
input wire [0 : 0] In13;
input wire [0 : 0] In14;
input wire [0 : 0] In15;
output wire [15 : 0] dout;

  xlconcat_v2_1_3_xlconcat #(
    .IN0_WIDTH(1),
    .IN1_WIDTH(1),
    .IN2_WIDTH(1),
    .IN3_WIDTH(1),
    .IN4_WIDTH(1),
    .IN5_WIDTH(1),
    .IN6_WIDTH(1),
    .IN7_WIDTH(1),
    .IN8_WIDTH(1),
    .IN9_WIDTH(1),
    .IN10_WIDTH(1),
    .IN11_WIDTH(1),
    .IN12_WIDTH(1),
    .IN13_WIDTH(1),
    .IN14_WIDTH(1),
    .IN15_WIDTH(1),
    .IN16_WIDTH(1),
    .IN17_WIDTH(1),
    .IN18_WIDTH(1),
    .IN19_WIDTH(1),
    .IN20_WIDTH(1),
    .IN21_WIDTH(1),
    .IN22_WIDTH(1),
    .IN23_WIDTH(1),
    .IN24_WIDTH(1),
    .IN25_WIDTH(1),
    .IN26_WIDTH(1),
    .IN27_WIDTH(1),
    .IN28_WIDTH(1),
    .IN29_WIDTH(1),
    .IN30_WIDTH(1),
    .IN31_WIDTH(1),
    .dout_width(16),
    .NUM_PORTS(16)
  ) inst (
    .In0(In0),
    .In1(In1),
    .In2(In2),
    .In3(In3),
    .In4(In4),
    .In5(In5),
    .In6(In6),
    .In7(In7),
    .In8(In8),
    .In9(In9),
    .In10(In10),
    .In11(In11),
    .In12(In12),
    .In13(In13),
    .In14(In14),
    .In15(In15),
    .In16(1'B0),
    .In17(1'B0),
    .In18(1'B0),
    .In19(1'B0),
    .In20(1'B0),
    .In21(1'B0),
    .In22(1'B0),
    .In23(1'B0),
    .In24(1'B0),
    .In25(1'B0),
    .In26(1'B0),
    .In27(1'B0),
    .In28(1'B0),
    .In29(1'B0),
    .In30(1'B0),
    .In31(1'B0),
    .dout(dout)
  );
endmodule
