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// IP VLNV: analog.com:user:util_cpack2:1.0
// IP Revision: 1

(* X_CORE_INFO = "util_cpack2,Vivado 2019.1" *)
(* CHECK_LICENSE_TYPE = "system_util_ad9361_adc_pack_0,util_cpack2,{}" *)
(* IP_DEFINITION_SOURCE = "package_project" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_util_ad9361_adc_pack_0 (
  clk,
  reset,
  enable_0,
  enable_1,
  enable_2,
  enable_3,
  fifo_wr_en,
  fifo_wr_overflow,
  fifo_wr_data_0,
  fifo_wr_data_1,
  fifo_wr_data_2,
  fifo_wr_data_3,
  packed_fifo_wr_en,
  packed_fifo_wr_overflow,
  packed_fifo_wr_sync,
  packed_fifo_wr_data
);

(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME packed_fifo_wr_signal_clock, ASSOCIATED_BUSIF packed_fifo_wr, ASSOCIATED_RESET reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_util_ad9361_divclk_0_clk_out, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 packed_fifo_wr_signal_clock CLK" *)
input wire clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME packed_fifo_wr_signal_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 packed_fifo_wr_signal_reset RST" *)
input wire reset;
input wire enable_0;
input wire enable_1;
input wire enable_2;
input wire enable_3;
input wire fifo_wr_en;
output wire fifo_wr_overflow;
input wire [15 : 0] fifo_wr_data_0;
input wire [15 : 0] fifo_wr_data_1;
input wire [15 : 0] fifo_wr_data_2;
input wire [15 : 0] fifo_wr_data_3;
(* X_INTERFACE_INFO = "analog.com:interface:fifo_wr:1.0 packed_fifo_wr EN" *)
output wire packed_fifo_wr_en;
(* X_INTERFACE_INFO = "analog.com:interface:fifo_wr:1.0 packed_fifo_wr OVERFLOW" *)
input wire packed_fifo_wr_overflow;
(* X_INTERFACE_INFO = "analog.com:interface:fifo_wr:1.0 packed_fifo_wr SYNC" *)
output wire packed_fifo_wr_sync;
(* X_INTERFACE_INFO = "analog.com:interface:fifo_wr:1.0 packed_fifo_wr DATA" *)
output wire [63 : 0] packed_fifo_wr_data;

  util_cpack2 #(
    .NUM_OF_CHANNELS(4),
    .SAMPLES_PER_CHANNEL(1),
    .SAMPLE_DATA_WIDTH(16)
  ) inst (
    .clk(clk),
    .reset(reset),
    .enable_0(enable_0),
    .enable_1(enable_1),
    .enable_2(enable_2),
    .enable_3(enable_3),
    .enable_4(1'B0),
    .enable_5(1'B0),
    .enable_6(1'B0),
    .enable_7(1'B0),
    .enable_8(1'B0),
    .enable_9(1'B0),
    .enable_10(1'B0),
    .enable_11(1'B0),
    .enable_12(1'B0),
    .enable_13(1'B0),
    .enable_14(1'B0),
    .enable_15(1'B0),
    .enable_16(1'B0),
    .enable_17(1'B0),
    .enable_18(1'B0),
    .enable_19(1'B0),
    .enable_20(1'B0),
    .enable_21(1'B0),
    .enable_22(1'B0),
    .enable_23(1'B0),
    .enable_24(1'B0),
    .enable_25(1'B0),
    .enable_26(1'B0),
    .enable_27(1'B0),
    .enable_28(1'B0),
    .enable_29(1'B0),
    .enable_30(1'B0),
    .enable_31(1'B0),
    .enable_32(1'B0),
    .enable_33(1'B0),
    .enable_34(1'B0),
    .enable_35(1'B0),
    .enable_36(1'B0),
    .enable_37(1'B0),
    .enable_38(1'B0),
    .enable_39(1'B0),
    .enable_40(1'B0),
    .enable_41(1'B0),
    .enable_42(1'B0),
    .enable_43(1'B0),
    .enable_44(1'B0),
    .enable_45(1'B0),
    .enable_46(1'B0),
    .enable_47(1'B0),
    .enable_48(1'B0),
    .enable_49(1'B0),
    .enable_50(1'B0),
    .enable_51(1'B0),
    .enable_52(1'B0),
    .enable_53(1'B0),
    .enable_54(1'B0),
    .enable_55(1'B0),
    .enable_56(1'B0),
    .enable_57(1'B0),
    .enable_58(1'B0),
    .enable_59(1'B0),
    .enable_60(1'B0),
    .enable_61(1'B0),
    .enable_62(1'B0),
    .enable_63(1'B0),
    .fifo_wr_en(fifo_wr_en),
    .fifo_wr_overflow(fifo_wr_overflow),
    .fifo_wr_data_0(fifo_wr_data_0),
    .fifo_wr_data_1(fifo_wr_data_1),
    .fifo_wr_data_2(fifo_wr_data_2),
    .fifo_wr_data_3(fifo_wr_data_3),
    .fifo_wr_data_4(16'B0),
    .fifo_wr_data_5(16'B0),
    .fifo_wr_data_6(16'B0),
    .fifo_wr_data_7(16'B0),
    .fifo_wr_data_8(16'B0),
    .fifo_wr_data_9(16'B0),
    .fifo_wr_data_10(16'B0),
    .fifo_wr_data_11(16'B0),
    .fifo_wr_data_12(16'B0),
    .fifo_wr_data_13(16'B0),
    .fifo_wr_data_14(16'B0),
    .fifo_wr_data_15(16'B0),
    .fifo_wr_data_16(16'B0),
    .fifo_wr_data_17(16'B0),
    .fifo_wr_data_18(16'B0),
    .fifo_wr_data_19(16'B0),
    .fifo_wr_data_20(16'B0),
    .fifo_wr_data_21(16'B0),
    .fifo_wr_data_22(16'B0),
    .fifo_wr_data_23(16'B0),
    .fifo_wr_data_24(16'B0),
    .fifo_wr_data_25(16'B0),
    .fifo_wr_data_26(16'B0),
    .fifo_wr_data_27(16'B0),
    .fifo_wr_data_28(16'B0),
    .fifo_wr_data_29(16'B0),
    .fifo_wr_data_30(16'B0),
    .fifo_wr_data_31(16'B0),
    .fifo_wr_data_32(16'B0),
    .fifo_wr_data_33(16'B0),
    .fifo_wr_data_34(16'B0),
    .fifo_wr_data_35(16'B0),
    .fifo_wr_data_36(16'B0),
    .fifo_wr_data_37(16'B0),
    .fifo_wr_data_38(16'B0),
    .fifo_wr_data_39(16'B0),
    .fifo_wr_data_40(16'B0),
    .fifo_wr_data_41(16'B0),
    .fifo_wr_data_42(16'B0),
    .fifo_wr_data_43(16'B0),
    .fifo_wr_data_44(16'B0),
    .fifo_wr_data_45(16'B0),
    .fifo_wr_data_46(16'B0),
    .fifo_wr_data_47(16'B0),
    .fifo_wr_data_48(16'B0),
    .fifo_wr_data_49(16'B0),
    .fifo_wr_data_50(16'B0),
    .fifo_wr_data_51(16'B0),
    .fifo_wr_data_52(16'B0),
    .fifo_wr_data_53(16'B0),
    .fifo_wr_data_54(16'B0),
    .fifo_wr_data_55(16'B0),
    .fifo_wr_data_56(16'B0),
    .fifo_wr_data_57(16'B0),
    .fifo_wr_data_58(16'B0),
    .fifo_wr_data_59(16'B0),
    .fifo_wr_data_60(16'B0),
    .fifo_wr_data_61(16'B0),
    .fifo_wr_data_62(16'B0),
    .fifo_wr_data_63(16'B0),
    .packed_fifo_wr_en(packed_fifo_wr_en),
    .packed_fifo_wr_overflow(packed_fifo_wr_overflow),
    .packed_fifo_wr_sync(packed_fifo_wr_sync),
    .packed_fifo_wr_data(packed_fifo_wr_data)
  );
endmodule
